Objective(S)

This section outlines the objectives of Lab Module 7, focusing on the design and verification of combinational CMOS logic gates.

Theory And Background

This section explores the design and verification of basic combinational CMOS logic gates, particularly 2-input NAND and NOR gates.

Combinational Cmos Logic Gate Design

The section outlines the fundamental principles and processes in designing combinational CMOS logic gates, specifically focusing on 2-input NAND and NOR gates, while emphasizing layout design, routing, and verification.

Layout Considerations For Multi-Transistor Gates

This section discusses the critical considerations for designing multi-transistor gates, including transistor stacking, routing, and design rule adherence.

Layout Design Rules Review And Application

This section focuses on the application of layout design rules in the context of combinational CMOS logic gates, emphasizing the verification processes essential for accurate circuit implementation.

Matching And Common Centroid Layouts (For Improved Performance)

This section introduces the concept of matching in digital gate layouts, emphasizing the importance of common centroid layouts and their role in minimizing mismatch and enhancing performance.

Physical Verification: Drc And Lvs

This section covers the importance of Design Rule Check (DRC) and Layout Versus Schematic (LVS) in the physical verification of CMOS layouts.

Post-Layout Simulation

Post-layout simulation validates and analyzes the performance of CMOS logic gates, accounting for parasitic effects from layout.

Pre-Lab Questions And Preparation

This section outlines essential pre-lab questions and preparations students must complete before participating in a lab focused on combinational CMOS logic gates.

Procedure/experimental Steps

This section outlines the detailed procedural steps for designing and verifying the layout of 2-input NAND and NOR CMOS logic gates.

Task 1: Schematic Capture Of 2-Input Nand Gate And Pre-Layout Simulation

This section outlines the steps for capturing the schematic of a 2-input NAND gate and performing pre-layout simulation.

Task 2: Full-Custom Layout Design Of 2-Input Nand Gate

This section focuses on the design and verification of a 2-input NAND gate layout, incorporating principles of CMOS layout design, routing, verification, and performance analysis.

Task 3: Physical Verification - Design Rule Check (Drc)

This section focuses on performing physical verification checks, specifically the Design Rule Check (DRC), to ensure the layout adheres to fabrication process rules.

Task 4: Physical Verification - Layout Versus Schematic (Lvs)

This section focuses on the critical step of Layout Versus Schematic (LVS) verification in semiconductor design, emphasizing the importance of comparing the physical layout with the intended schematic.

Task 5: Post-Layout Simulation For Nand Gate

This section discusses the process and significance of post-layout simulation for NAND gates in VLSI design.

Task 6: Repeat For 2-Input Nor Gate

In this section, students repeat tasks to design, verify, and analyze the performance of a 2-input NOR gate, extending their understanding of combinational CMOS logic gates.

Post-Lab Questions And Analysis

This section focuses on the analysis and reflection required after completing the lab on combinational CMOS logic gate layouts, specifically NAND and NOR gates.

Deliverables

This section outlines the key deliverables expected from students after completing the lab module on CMOS logic gate layout design and verification.