The Instruction Set Architecture (ISA) is the abstract definition of a computer's CPU that is visible to a programmer or a compiler. It represents the contract between the hardware and the software. The ISA specifies what the CPU can do, without necessarily detailing how it does it. It is the crucial interface that allows software written for a particular ISA (e.g., ARMv7, x86-64, RISC-V) to run correctly on any CPU hardware implementation that adheres to that ISA, regardless of the internal micro-architectural differences.

Key elements defined by an ISA include:
- Instruction Set: The complete collection of machine instructions that the CPU can execute, including their mnemonics and binary opcodes.
- Instruction Formats: The precise bit patterns of all instructions, indicating the position and meaning of opcode, operand fields, etc.
- Addressing Modes: All the ways in which the CPU can calculate the effective memory address of an operand.
- Registers: The set of programmer-visible CPU registers, including general-purpose registers, special-purpose registers (like Program Counter, Stack Pointer), and status/flag registers.
- Data Types: The data types the CPU can directly operate on (e.g., 8-bit bytes, 16-bit words, 32-bit integers, floating-point numbers).
- Memory Organization: How memory is accessed (e.g., byte-addressable, word-addressable) and the endianness (byte order).
- Privilege Levels and Exception Handling: How the CPU manages different operating modes (e.g., user mode, kernel mode) and responds to interrupts and exceptions.

The instruction format is the layout of bits within a machine instruction. It defines how the instruction is encoded in binary for the CPU to understand.

• Fixed vs. Variable Length Instructions:
• Fixed-Length Instructions: All instructions in the processor's instruction set occupy the same number of bits (e.g., all instructions are 16-bit, 32-bit, or 64-bit).
  • Advantages: Simpler hardware design for fetching and decoding instructions. This regularity allows for more efficient and faster pipelining, where multiple instructions are processed concurrently in different stages of the CPU pipeline. It also simplifies memory alignment and caching.
  • Disadvantages: Can be less code-dense. If a simple operation requires only a few bits for its opcode and operands, the remaining bits in a fixed-length instruction are unused, leading to wasted memory space. Conversely, if a complex operation requires many operands or a large immediate value, it might be difficult to fit all information within the fixed length.
  • Example Architectures: ARM (standard 32-bit instructions), MIPS, RISC-V (standard 32-bit instructions, though compressed 16-bit forms exist for code density).
• Variable-Length Instructions: Instructions can have different sizes, meaning some instructions might be 8 bits, others 16 bits, 32 bits, or even longer, depending on the complexity of the operation and the number/type of operands.
  • Advantages: More code-dense. This allows for smaller program binaries, which is particularly beneficial in memory-constrained embedded systems. Common, simple operations can use very short instructions, while less frequent, complex operations can use longer instructions to include more information.
  • Disadvantages: More complex hardware design for instruction fetching and decoding. The CPU must first decode part of an instruction to determine its total length before fetching the next instruction, which can complicate pipelining and reduce execution speed.
  • Example Architectures: Intel x86 (instructions can range from 1 to 15 bytes), VAX.

This classification refers to the number of explicit operand addresses that are specified directly within the instruction. The addresses can refer to registers or memory locations.

• 3-Address Instructions:
• Concept: The instruction explicitly specifies three operands: two source operands and a distinct destination operand.
• Example: ADD R1, R2, R3 (Meaning: R1 = R2 + R3). Here, R2 and R3 are source addresses, and R1 is the destination address.
• Implications: Allows for very direct translation of high-level language expressions (e.g., A = B + C). Intermediate results rarely need to be stored back to memory or temporarily moved between registers. This can lead to fewer instructions for a given computation. However, it requires more bits within the instruction to encode all three addresses, potentially leading to longer instruction formats.
• 2-Address Instructions:
• Concept: The instruction explicitly specifies two operands, where one of the operands serves as both a source and the destination. The operation overwrites one of the source operands with the result.
• Example: ADD R1, R2 (Meaning: R1 = R1 + R2). Here, R1 is both a source and the destination, and R2 is a source.
• Implications: More compact instruction format compared to 3-address instructions, as fewer address bits are needed. This is a very common approach in modern processors. However, if the original value of the source/destination operand needs to be preserved, an additional MOVE instruction might be required before the operation.
• 1-Address Instructions (Accumulator-based):
• Concept: The instruction explicitly specifies only one operand. The other operand, and typically the implicit destination for the result, is a special, dedicated CPU register called the accumulator (ACC).
• Example: ADD R2 (Meaning: ACC = ACC + R2). LOAD 1000 (Meaning: ACC = Memory[1000]).
• Implications: Very compact instruction format due to requiring only one address field. However, programs require more instructions to perform complex calculations, as every operation implicitly involves the accumulator, necessitating frequent LOAD and STORE operations to manage intermediate results. Less common in modern general-purpose CPUs, but can be found in simpler microcontrollers or older architectures.
• 0-Address Instructions (Stack-based):
• Concept: Instructions have no explicit operand addresses. All operations implicitly act on the values located at the top of a hardware-managed stack. Operands are POPped from the stack, the operation is performed, and the result is PUSHed back onto the stack.
• Example: ADD (Pops the top two elements from the stack, adds them, and PUSHes the sum back onto the stack).
• Implications: Extremely compact instruction format. Requires a highly efficient stack implementation in hardware. The sequence of operations can sometimes be less intuitive for human programmers (reverse Polish notation). Used in some specialized processors, calculators, and virtual machine architectures (e.g., Java Virtual Machine, some Forth systems).

Regardless of its length or the number of addresses it specifies, a machine instruction is fundamentally a binary word structured into distinct fields:

• Opcode Field: This is the most crucial part of the instruction. It contains a unique binary code that tells the CPU exactly what operation to perform (e.g., 001010 for ADD, 110100 for LOAD). The length of the opcode field determines the maximum number of distinct instructions in the ISA.
• Operand Fields: These fields provide information about the data that the operation will use or modify. They can encode:
• Register Address: A small binary number that uniquely identifies one of the CPU's general-purpose registers (e.g., 000 for R0, 001 for R1). The number of bits in this field depends on the total number of registers.
• Memory Address: For instructions that directly access memory, this field contains the full or partial memory address of the operand. The size of this field determines the maximum directly addressable memory space.
• Immediate Value: A constant numerical value (literal) that is embedded directly within the instruction itself. This value is used as an operand without needing to be fetched from a register or memory. The size of this field limits the range of immediate values that can be used.
• Addressing Mode Specifics: Additional bits might be present to specify the particular addressing mode to be used, or to provide offsets, or to select between different sizes of operands (byte, word, double word).

An addressing mode defines the rule or algorithm by which the CPU determines the actual physical memory location (the effective address) of an operand. Different addressing modes provide flexibility and efficiency in accessing various types of data, implementing data structures, and supporting different programming constructs.

• Immediate Addressing:
• Calculation: The operand's value is the address itself. No calculation is needed to find the operand's location; the operand's value is directly available within the instruction.
• Example: ADD R1, #5 (Add the integer 5 to the content of R1). Here, #5 is the immediate operand.
• Use Cases: Loading constant values into registers, initializing variables, performing operations with small fixed numerical values. It's the fastest way to get data into a register because no memory access is required.
• Register Addressing:
• Calculation: The operand's value is located directly in a specified CPU general-purpose register. The instruction contains the identifier (name) of the register.
• Example: ADD R1, R2 (Add the content of R2 to R1). R1 and R2 are both operands accessed via register addressing.
• Use Cases: Extremely fast data access as registers are the fastest storage available to the CPU. Used for holding intermediate results of calculations, loop counters, and frequently accessed variables.
• Absolute (Direct) Addressing:
• Calculation: The instruction explicitly contains the complete and unambiguous physical memory address where the operand is stored.
• Example: LOAD R1, 0x1000 (Load the value from memory address 0x1000 into R1). Here, 0x1000 is the absolute address.
• Use Cases: Accessing global variables whose addresses are fixed at compile time, reading from or writing to specific, known memory-mapped I/O device registers.
• Limitations: Requires sufficient bits in the instruction's address field to cover the entire memory space, which can be problematic for large memory systems. Programs using absolute addresses are generally not 'relocatable' – they must be loaded into specific memory locations to work correctly.
• Indirect Addressing:
• Concept: The instruction does not hold the operand's value or its direct address. Instead, it holds the address of a location (either a CPU register or a memory location) that contains the effective address of the operand. This is analogous to a pointer in high-level languages.
• Register Indirect Addressing:
  • Calculation: The effective address of the operand is the value currently held in a specified CPU register.
  • Example: LOAD R1, (R2) (Load the value from the memory location whose address is stored in R2, into R1). The parentheses () typically denote register indirect addressing.
  • Use Cases: Implementing pointers, traversing data structures (like linked lists), passing parameters by reference, and flexible access to array elements where the register holds the base address.
• Memory Indirect Addressing:
  • Calculation: The effective address of the operand is stored in a specified memory location. This requires two memory accesses: one to fetch the address from memory, and a second to fetch the actual operand from that address.
  • Example: LOAD R1, @2000 (Load the value from the memory location whose address is stored at memory location 2000, into R1). The @ symbol commonly denotes memory indirect.
  • Use Cases: Less common due to performance penalty (two memory accesses), but can be used for very flexible pointer-like operations where the pointer itself is stored in memory.
• Indexed Addressing:
• Calculation: The effective address of the operand is computed by adding a constant offset (or displacement) to the content of a specified index register (or base register).
• Formula: Effective Address = [Content of Index Register] + Offset
• Example: LOAD R1, 100(R2) (Load the value from the memory location whose address is calculated as (Content of R2) + 100, into R1).
• Use Cases: Extremely efficient and widely used for accessing elements within arrays. The index register typically holds the starting (base) address of the array, and the offset changes for each element (e.g., 0 for the first element, size_of_element for the second, etc.). Also useful for accessing fields within records or structures.
• Relative Addressing (PC-Relative Addressing):
• Calculation: The effective address of the operand (typically the target of a branch or jump instruction) is computed by adding a constant offset (or displacement) to the current value of the Program Counter (PC).
• Formula: Effective Address = [Content of PC] + Offset
• Example: BRANCH 50 (Jump to the instruction located 50 bytes after the current instruction). If the current PC is 0x100, the target address becomes 0x100 + 50 = 0x150.
• Use Cases: Primarily used for branch and jump instructions within a program. It is crucial for creating position-independent code (PIC). PIC means the program can be loaded and executed correctly at any arbitrary memory address without needing to be modified, because all its internal jumps are relative to the PC, not to absolute memory locations. This is vital for shared libraries, dynamic loading, and programs stored in ROM.
• Autoincrement/Autodecrement Addressing:
• Concept: These are specialized variants of register indirect addressing that combine operand access with automatic modification (increment or decrement) of the address-holding register. This is highly efficient for sequential data access.
• Autoincrement:
  • Calculation: The operand is accessed at the address currently stored in the specified register. After the access, the content of the register is automatically incremented by the size of the operand (e.g., by 1 for byte access, by 4 for word access).
  • Example: LOAD R1, (R2)+ (Load the value from the address in R2 into R1, then increment R2).
• Autodecrement:
  • Calculation: The content of the specified register is first automatically decremented by the size of the operand. Then, the operand is accessed at this new, decremented address.
  • Example: STORE -(R2), R1 (Decrement R2, then store the content of R1 to the memory address now in R2).
• Use Cases: Extremely efficient for iterating through arrays (e.g., processing elements sequentially), implementing loops that traverse data, and especially for managing stacks, as the register (often the Stack Pointer) naturally moves to the next or previous element during PUSH and POP operations.