15.2.2. Physically Indexed Physically Tagged Cache

In a physically indexed physically tagged cache, the physical address translation occurs before cache access. This means that a virtual address is transformed to a physical address using a Translation Lookaside Buffer (TLB) before accessing the cache. This method illustrates the architecture of the Intrinsity FastMATH example.

In this type of cache, before we can access data in the cache, we need to find the corresponding physical address from a virtual address. This transformation is done using a TLB. If there's a match in the TLB, the physical address is retrieved and the cache can then be accessed. This is a critical point because any delays in TLB lookups affect overall cache access time, making it more complicated if a TLB miss occurs, as it requires accessing the main memory.

You can think of the TLB as a librarian who remembers where specific books are shelved in a large library. If you know the book's name (the virtual address), you ask the librarian where it is (the TLB). If the librarian remembers (a TLB hit), you go directly to the shelf (access the cache). If she doesn't remember (a TLB miss), you have to go through the entire library (main memory) to find the book's location, which takes much longer.

The issue with the TLB being in the critical path is that even if the required data is in the cache, the system must still check the TLB, leading to multiple cycles of access when there is a TLB miss, significantly increasing access time.

Having the TLB in the critical path means that it can slow down data access significantly. If the item is in the cache but the TLB cannot provide the right physical address quickly, users experience delays. If the data isn't quickly found in the TLB, the system goes to main memory to retrieve necessary page information. This back-and-forth can lead to significant wait times, which is a major drawback of this architecture.

Imagine if every time you wanted to send a gift (data) to a friend (cache), you had to first check the address record (TLB) to confirm the address. If you couldn’t find it immediately, you'd have to go back to your home (main memory) to get it. Every time this happens, there’s a delay in sending the gift, increasing frustration.

The main advantage of this caching scheme is that cache contents remain valid as long as the page table isn’t changed.

In environments where the page table remains consistent, the data stored in the cache can be reliably used across multiple accesses, providing efficient performance benefits. Without frequent updates or changes to the page table, this scheme can deliver quick access to frequently used data, avoiding unnecessary reloads from slower memory sources.

Imagine a storage closet (cache) filled with items (data) that you frequently use. If you make sure to organize this closet in a way that everything stays in place while you are not changing items around (stable page table), accessing what you need becomes quick and efficient, making your work (processing tasks) smoother.

To alleviate the issues with TLB being in the critical path, methods of cache indexing that reduce reliance on TLB access are considered, leading to innovations like virtually indexed virtually tagged caches.

Because the TLB can slow down cache access significantly, new caching methods that involve using virtual addresses directly were developed. These methods directly index into cache without needing TLB lookup for cache hits, though they bring their own set of challenges like cache flushing and handling data consistency.

If the librarian (TLB) were not needed every time to find your book (data in cache), you could directly access the bookshelves, making the process much quicker. However, if different people might take out the same book at the same time (cache misses), then issues might arise regarding which version of the book is valid.

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