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3 cards from this section. Quick, good the night before a test.
What are the three parts of a memory address in a direct mapped cache?
Think about how memory addresses need to be structured for cache access.
What happens during a cache hit?
Consider the benefits of having essential information ready.
What does a cache hit indicate?
Think about why we use cache memory at all.
True or False: A cache miss means the data must be fetched from the cache.
Consider the definition of a miss.
Design a direct mapped cache with at least 8 cache lines. Explain how you would handle accessing elements from an array and how locality of reference would impact performance.
Consider how array access patterns are often sequential.
Explain the effects of increasing the size of cache memory on the miss rates. Provide a formula or reasoning to support your explanation.
Reflect on how more cache lines can hold more frequently accessed data.
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