Practice Direct-mapped Caches: Misses, Writes and Performance - 4.2 | 4. Direct-mapped Caches: Misses, Writes and Performance | Computer Organisation and Architecture - Vol 3
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Practice Questions

Test your understanding with targeted questions related to the topic.

Question 1

Easy

What does SRAM stand for?

💡 Hint: Think about the 'S' in SRAM.

Question 2

Easy

What is a cache hit?

💡 Hint: Reflect on what happens during a successful data retrieval.

Practice 4 more questions and get performance evaluation

Interactive Quizzes

Engage in quick quizzes to reinforce what you've learned and check your comprehension.

Question 1

What is the access time of SRAM?

  • 0.5 to 2.5 nanoseconds
  • 50 to 70 nanoseconds
  • 5 to 20 milliseconds

💡 Hint: Remember the timing details given for SRAM.

Question 2

True or False: A cache miss occurs when requested data is not found in the cache.

  • True
  • False

💡 Hint: Recall the definition of a cache miss given in class.

Solve and get performance evaluation

Challenge Problems

Push your limits with challenges.

Question 1

Given a cache with 16 lines and a block size of 4 words, calculate the direct mapping for memory block 12.

💡 Hint: Use the mapping function for cache lines.

Question 2

Create a scenario with four memory accesses: 0, 4, 8, and 12. What will the hit/miss ratio be if they are stored in a direct-mapped cache with 4 lines?

💡 Hint: Visualize the block's mapping to cache lines and identify miss occurrences.

Challenge and get performance evaluation