Review Questions

Multivibrators are circuits that create an oscillating signal, and they come in three types: bistable, monostable, and astable. Bistable multivibrators can maintain a stable state indefinitely until triggered to change, resembling flip-flops closely. Monostable multivibrators temporarily change state in response to an input pulse, returning to their original state after a set time. Astable multivibrators continuously oscillate between two states, producing a square wave output.

A flip-flop is a digital memory circuit that can hold one bit of data; it's known for its bistable nature. An R-S flip-flop uses two inputs, R (reset) and S (set), which can set or reset the output Q. When both R and S are inactive (0), Q hold its state. If S is activated (1), Q becomes 1; if R is activated (1), Q resets to 0. There's a critical condition (1, 1) that's often marked invalid because it creates ambiguity.

A clocked R-S flip-flop uses a clock signal to control the state transition that occurs based on R and S inputs, which are active low. When the clock transitions to a negative edge, the flip-flop can read R and S inputs. If R is LOW, the output resets to 0. If S is LOW, the flip-flop sets Q to 1. If both inputs are HIGH when the clock transitions, the state remains unchanged. The truth table emphasizes the stable states and invalid states.

A clocked J-K flip-flop is an enhancement over the R-S flip-flop that eliminates the invalid state (where both R and S are active). In a J-K flip-flop, the inputs J and K can toggle the output Q. When both J and K are active simultaneously, instead of entering an undefined state, the output toggles, which allows for more versatile operations in circuits.

Synchronous inputs require a clock signal to determine when to act, while asynchronous inputs can change independently of the clock. Level-triggered flip-flops change states based on the input level as long as the clock is high, whereas edge-triggered flip-flops change states only on the clock edge (rising or falling). Active LOW means that a signal performs its function when low (0), and active HIGH indicates its function occurs when high (1).

Set-up time is the minimum time the inputs must be stable before the clock edge, while hold time is how long the inputs must remain stable after the clock edge. Propagation delay is the time it takes for an input change to affect the output. Maximum clock frequency defines the highest frequency that can be applied to the clock input for reliable operation.

Truth tables provide a clear view of how each J-K flip-flop reacts to its inputs. For part (a), when J is high and K is low during a positive edge, the output will set to 1. The logic behaves the opposite for part (b) where active LOW inputs dictate the states when clocked on the negative edge, demonstrating how the outputs toggle based on J and K inputs and the clock signal. All scenarios need to be mapped including the invalid states.

The race problem occurs in flip-flops when inputs change too quickly relative to the clock signal, potentially leading to unpredictable output states. A master-slave configuration addresses this issue by using two flip-flops: the master captures the input on the clock edge while the slave changes output on the next clock edge, thus isolating the changes and preventing contention during state transitions.

A D latch is level-triggered, meaning its output can change as long as the enable signal is active. On the other hand, a D flip-flop is edge-triggered, changing output only at a specific moment determined by the clock signal. This distinction leads to different operational characteristics in circuits; latches can be more flexible but also susceptible to unwanted input changes.

A function table shows the relationship between inputs and outputs, mapping different states based on defined conditions. For the negative edge-triggered D flip-flop, the output reflects the D input only when the clock transitions negatively. In contrast, for the D latch with active LOW ENABLE, the output follows the D input as long as ENABLE is active low, illustrating the difference in response to inputs over time.

By connecting the J-K flip-flop with specific inputs, it can emulate different types of flip-flops. For instance, to create a D flip-flop, connect J to D and K to the negation of D. To configure it as a T flip-flop, connect J and K to the same input T, allowing the output to toggle on each clock pulse. This versatility illustrates how the J-K flip-flop can be adapted for various functions within digital circuits.

A D flip-flop can be angled to detect the order of events by applying two signals (A and B) to its inputs. The edge of one signal can trigger the flip-flop, capturing the signal state. Subsequent changes can then be compared based on the output of the flip-flop indicating which signal edged first. This helps in timing analysis and synchronization tasks.