These techniques are central to PCB and chip design.

• Intelligent Component Selection and Package Optimization:
• Integrated Solutions: Prioritizing MCUs that integrate many necessary peripherals (ADCs, DACs, communication interfaces, sometimes even wireless modules) directly on-chip, reducing the need for external components.
• Package Types: Choosing smaller chip package types (e.g., QFN, BGA, CSP, WLCSP) which have smaller footprints compared to larger, older packages (e.g., TQFP, DIP). This directly impacts PCB area.
• Multi-Chip Modules (MCMs) and Package-on-Package (PoP): Stacking multiple dies or complete packages vertically, significantly reducing the overall footprint (e.g., stacking Flash memory directly on top of the processor package).
• Chiplet Architectures: Designing a complex SoC as multiple smaller 'chiplets' connected on an interposer, allowing for mixing and matching different process technologies and improving yield.
• High-Density Integration (SoC Design):
• Benefits: Integrating CPU, memory controllers, peripherals, and custom accelerators onto a single die drastically reduces external wiring, improves internal communication speed, and lowers power consumption (due to shorter traces and fewer off-chip drivers). This also reduces BOM count significantly.
• NRE Consideration: While reducing per-unit cost for high volume, custom SoC design incurs very high NRE.
• Resource Sharing and Multiplexing: Designing hardware to allow a single physical resource (e.g., an ADC, a serial port) to be shared by multiple logical functions or sensors, managed by software. This reduces the number of dedicated peripheral blocks or external components.
• Advanced PCB Layout Optimization:
• Reduced Layer Count: Using fewer PCB layers (e.g., 2-layer vs. 4-layer) significantly reduces manufacturing cost, but requires more careful routing.
• High-Density Routing: Using smaller trace widths, spacing, and micro-vias to route signals in a smaller area.
• Component Placement: Arranging components tightly and strategically to minimize the total board area while considering signal integrity, thermal dissipation, and manufacturability.
• Power and Ground Planes: Using dedicated layers for power and ground can reduce noise and simplify routing.
• Design for Manufacturability (DFM) and Design for Testability (DFT):
• DFM: Applying design rules to ensure the product can be manufactured efficiently and with high yield. This includes considering component spacing, pad sizes, solder mask clearances, and assembly process limitations. Poor DFM leads to higher manufacturing costs and rejects.
• DFT: Incorporating features to make testing easier and faster. This includes scan chains (connecting all flip-flops into a serial chain for easy test pattern loading/unloading), JTAG (Joint Test Action Group) interfaces for boundary scan and in-circuit testing, and Built-in Self-Test (BIST) circuits within IP blocks. Efficient testing reduces manufacturing test time and costs.

Software's memory footprint has a direct impact on the cost of onboard memory.

• Aggressive Code Size Optimization:
• Compiler Optimizations for Size: Using specific compiler flags (e.g., -Os in GCC) that prioritize minimal code size over speed. This might involve avoiding function inlining, using smaller integer types, and eliminating redundant instructions.
• Algorithmic and Data Structure Compactness: Choosing algorithms that have smaller instruction footprints and data structures that require less memory.
• Removing Unused Code and Data: Utilizing linker optimizations (e.g., garbage collection, dead code stripping) to remove functions and global variables that are never referenced. Carefully configuring RTOSes and libraries to exclude unneeded features.
• Code Overlays: For very large applications on small memory devices, only loading portions of the code into RAM as needed from non-volatile storage, replacing previously loaded sections. This increases complexity but reduces RAM requirements.
• Lean RTOS/Library Selection and Configuration:
• Bare-metal Programming: For very simple applications, completely avoiding an RTOS to save all associated code and data memory.
• Lightweight RTOS: Choosing a compact RTOS (e.g., FreeRTOS, µC/OS) and meticulously configuring it to include only essential features (e.g., only specific synchronization primitives, minimal task count).
• Static vs. Dynamic Linking: Static linking embeds all library code directly into the executable, potentially increasing executable size but avoiding runtime dependency issues. Dynamic linking (shared libraries) can save space if multiple executables use the same library but adds runtime overhead and complexity.
• Bootloader Size Optimization: The bootloader, which initializes the system and loads the main application, must be very small to fit into a small, often fixed-size, portion of non-volatile memory (e.g., ROM or a small Flash block). Every byte counts here.