5.2.2. FPGA-Based FIR Filter Example

Finite Impulse Response (FIR) filters are commonly used in DSP applications for signal smoothing or noise reduction.

FIR filters are a type of filter used in digital signal processing (DSP). They work by taking a finite number of previous input values and using them to calculate the current output value. The 'finite impulse response' means that the output depends only on the current and a limited number of past inputs, making them stable and easy to design.

Think of FIR filters like a coffee filter: it only lets through some parts of the coffee, the 'good' parts, removing the grit. Similarly, an FIR filter removes unwanted noise from signals while letting the desired information through.

Below is a simple example of how to implement an FIR filter on an FPGA using VHDL.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY FIR_FILTER IS
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- Input signal
Y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) -- Filtered output
);
END ENTITY FIR_FILTER;
ARCHITECTURE behavior OF FIR_FILTER IS
TYPE coeff_array IS ARRAY (0 TO 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); -- Coefficients of the filter
SIGNAL coeffs : coeff_array := ("0000000000000001", "0000000000000010",
"0000000000000100", "0000000000000010", "0000000000000001");
SIGNAL shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others => '0');
SIGNAL acc : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
BEGIN
PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
shift_reg <= (others => '0');
acc <= (others => '0');
ELSIF (CLK'event AND CLK = '1') THEN
shift_reg <= X & shift_reg(15 DOWNTO 1);
acc <= coeffs(0) * shift_reg(0) + coeffs(1) * shift_reg(1) + coeffs(2) * shift_reg(2) + coeffs(3) * shift_reg(3) + coeffs(4) * shift_reg(4);
Y <= acc(15 DOWNTO 0); -- Output the filtered signal
END IF;
END PROCESS;
END ARCHITECTURE behavior;

The VHDL code provided describes how to implement a simple FIR filter on an FPGA. The design includes components like an input signal (X), an output signal (Y), coefficients for the filter, a shift register to store input values, and an accumulator to calculate the output. The process defined in the code activates on clock signals. When the system resets, the values are cleared, but on each clock cycle, the new input gets shifted into the register, and the output is calculated by multiplying the stored values with the coefficients.

Imagine a chef preparing a smoothie. Each time they add a new fruit (the input signal), they blend it together with what's already in the blender (the shift register). The engineer has a recipe (the coefficients) that tells the chef how much of each fruit to add (the multiplication step) to get the perfect flavor (the filtered output).

This example implements a simple 5-tap FIR filter. The filter coefficients are hardcoded in the design, and the signal X is processed through a shift register and accumulator to produce the output signal Y.

In this FIR filter implementation, the term '5-tap' refers to the number of coefficients used to process the input signal. The hardcoding of coefficients means they are predefined in the design. During operation, the input signal (X) is shifted into the shift register with each clock cycle, and the output (Y) is generated by summing the products of the coefficients and the corresponding shifted input values. This provides a smoothed or filtered output based on the given input.

Using the smoothie analogy again, think of the five ingredients as specific fruits. As the chef adds each ingredient, they ensure the correct amount based on the recipe (coefficients). By synergizing these ingredients, they create a blended output that tastes better than any individual fruit—this symbolizes the FIR filter’s ability to enhance the quality of the original input signal.

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