1. Interfacing Schematic for DAC0808:
2. Connect DAC0808 D0-D7 to the microprocessor's D0-D7 data bus.
3. Connect the V_REF+ pin to +5V (or desired reference voltage).
4. Connect the V_REF- pin to ground.
5. Connect the Power Supply pins: VCC to +5V, VEE to -5V (or ground if using single supply mode).
6. Connect I_OUT to an external current-to-voltage converter circuit using an op-amp (e.g., LM741) and a feedback resistor. A common configuration uses a 5k Ohm feedback resistor with V_REF = +5V.

Output Voltage (V_OUT_OPAMP) = -I_OUT * R_F (where I_OUT is the DAC current output and R_F is the feedback resistor).

• I_OUT = I_REF * (Digital Input / 256) where I_REF = V_REF / R_REF (R_REF is often an internal resistor or an external resistor on V_REF pin). For DAC0808, I_REF = V_REF / 10k Ohm.
• So, V_OUT_OPAMP = - (V_REF / 10k Ohm) * (Digital Input / 256) * R_F.

If V_REF = 5V and R_F = 5k Ohm, V_OUT_OPAMP = - (5V / 10k) * (Digital Input / 256) * 5k = - (0.5mA) * (Digital Input / 256) * 5k = - (2.5 * Digital Input / 256).

• To get positive voltage, either invert the op-amp output or use I_OUT (complementary output) with an op-amp. Most trainers have internal op-amps for DAC.
• I/O Address Decoding: Design a simple I/O address decoder to generate a Chip Select (overlineCS) for the DAC. For example, assign DAC to I/O address 40H.
• Connect A6 of 8085/8086 to a gate, and combine with IO/overlineM (high) and overlineRD (high, as it's a write operation) to create overlineCS.
  For 8085: Use A6 and IO/overlineM (inverted) through a NAND gate, and then connect this to the DAC's CS. For a fixed port, say 40H, use A6=1, A5=0, A4=0, A3=0, A2=0, A1=0, A0=0. A simple decode could be A6 ORed with inverters of lower address lines. For simplicity, many trainers connect a DAC to a fixed port, say 40H, without complex external decoding. We'll assume a port address.

1. Assembly Program for Ramp/Staircase Waveform (8085/8086 example):
2. Aim: Generate a linearly increasing analog voltage output (staircase waveform) by sending incremental digital values to the DAC.
3. Microprocessor: 8085 (example, similar logic for 8086)
4. Port Address: Assume DAC is interfaced at Port 40H.

Assembly Code:

; 8085 Assembly Code for Ramp Waveform Generation
ORG 0000H
MVI A, 00H ; Initialize Accumulator with 0
LOOP:
OUT 40H ; Output A to DAC (Port 40H)
; DAC converts this digital value to an analog voltage
INR A ; Increment A
JNZ LOOP ; Repeat until A overflows (goes from FFH to 00H)
HLT ; Halt

1. Interfacing Schematic for ADC0804:
2. Connect ADC0804 D0-D7 to the microprocessor's D0-D7 data bus.
3. Connect VIN+ to the output of a potentiometer (variable voltage source, 0-5V). Connect VIN- to ground.
4. Connect V_REF/2 to +2.5V (for a 0-5V input range, V_REF = 5V. If V_REF is tied to VCC, it sets the max input). Typically, V_REF/2 is connected to VCC/2 or a dedicated 2.5V source. If V_REF is left open, it defaults to VCC.
5. Provide a clock source: For internal clock, connect 10k Ohm resistor between CLK R and CLK IN, and 150 pF capacitor between CLK IN and ground.
6. Connect Power Supply pins: VCC to +5V, GND to ground.
7. Control Signals:
8. overlineCS (Chip Select): Connect to I/O address decode output (e.g., Port 41H).
9. overlineRD (Read): Connect to microprocessor's overlineRD signal (for I/O read).
10. overlineWR (Write): Connect to microprocessor's overlineWR signal (for I/O write).
11. INTR (Interrupt): Connect to a status bit that the microprocessor can poll (e.g., a data line from an input port). For simple polling, connect INTR to D0 or D7 of an input port and read that port. Alternatively, use a ready pin if the trainer kit has one.
12. Output Display: Connect D0-D7 of the ADC to 8 LEDs with current limiting resistors, or to an LCD module for display.

1. Assembly Program for ADC Reading and Display (8085/8086 example):
2. Aim: Read analog voltage from potentiometer, convert to digital, and display on LEDs/LCD.
3. Microprocessor: 8085 (example, similar logic for 8086)
4. Port Addresses: Assume ADC overlineWR is at Port 41H (dummy write to start conversion), and ADC overlineRD data is at Port 41H (actual read). Assume INTR is connected to bit D7 of Input Port 42H.

Assembly Code:

; 8085 Assembly Code for ADC Read and Display
ORG 0000H
; Initialize (if necessary, for LCD or LED segment drivers)
; For direct LED connection, no special init needed
START_CONVERSION:
MVI A, 00H ; Dummy data
OUT 41H ; Send pulse to ADC WR to start conversion.
; This OUT instruction asserts WR (low) and selects port 41H
; (assuming 41H is decoded for ADC WR)
WAIT_FOR_CONVERSION:
IN 42H ; Read status of INTR (e.g., from D7 of Port 42H)
ANI 80H ; Mask all bits except D7 (INTR connected to D7)
JNZ WAIT_FOR_CONVERSION ; Loop until INTR goes low (D7 becomes 0)
; If INTR is active low, it means D7 should be 0.
; So, JNZ means "If D7 is NOT 0, keep waiting"
READ_ADC_DATA:
IN 41H ; Read digital data from ADC (Port 41H)
; This IN instruction asserts RD (low) and selects port 41H
; (assuming 41H is decoded for ADC RD)
MOV B, A ; Store the digital value in B register (for observation/display)
; Optional: Display B on LEDs or LCD
; If LEDs connected directly to data bus for output (e.g., through a latch)
; OUT LED_PORT ; Replace LED_PORT with actual output port for LEDs
HLT ; Halt
; Consider a loop to continuously read and display if desired.
; JMP START_CONVERSION ; Uncomment for continuous operation