Procedure/Experimental Steps - 4 | Lab Module 1: Introduction to the EDA Environment and MOS | VLSI Design Lab
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4 - Procedure/Experimental Steps

Practice

Interactive Audio Lesson

Listen to a student-teacher conversation explaining the topic in a relatable way.

Introduction to EDA Environment

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0:00
Teacher
Teacher

Welcome, everyone! Today we'll start with understanding the EDA environment. Why do you think EDA tools are crucial in VLSI design?

Student 1
Student 1

I think they help automate the design process, making it faster and more accurate.

Teacher
Teacher

Exactly! EDA tools simplify complex processes. Let's explore how to log in to our lab workstation. Can anyone share the steps?

Student 2
Student 2

We first power on the workstation and then use our username and password to log in.

Teacher
Teacher

Correct! Once logged in, we navigate to our home directory. Who can tell me how to create our lab directory?

Student 3
Student 3

By using the command 'mkdir -p vlsi_lab/lab1_mos_char'.

Teacher
Teacher

Right! Remember, proper directory management is key in EDA environments. Let's summarize today's key points: EDA tools streamline design and we create project directories for organized workflows.

Schematic Capture for NMOS

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0:00
Teacher
Teacher

Now that we are set up in the EDA environment, let’s jump into schematic capture. What is the first step when starting to build an NMOS test bench?

Student 1
Student 1

We need to place an NMOS transistor on the schematic canvas.

Teacher
Teacher

Spot on! After placing the transistor, we need to set its parameters. Can anyone remind us of the typical dimensions for NMOS?

Student 4
Student 4

Width should be around 500n and length around 180n.

Teacher
Teacher

Exactly! Setting these parameters correctly is essential. Let's discuss how we wire the test bench next. What should we connect the source terminal to?

Student 2
Student 2

It should be connected to the dedicated wire for 'src'.

Teacher
Teacher

Great job! Documenting your connections is crucial before moving to simulation. Today’s summary: Start by placing the NMOS, set its dimensions, and correctly wire the configuration.

Simulating NMOS I-V Characteristics

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0:00
Teacher
Teacher

Let’s move on to simulating the NMOS I-V characteristics. Who can tell me how we initiate the simulation environment?

Student 3
Student 3

We launch from the schematic window using the simulation environment options!

Teacher
Teacher

Correct! Next, we need to set the analysis type. What type of analysis comes next?

Student 1
Student 1

DC Analysis!

Teacher
Teacher

Exactly, and we should define the sweep parameters for VDS. What values do we consider for the sweep range?

Student 4
Student 4

Start from 0V to VDD, like 1.8V or 3.3V.

Teacher
Teacher

Very good! Lastly, we must remember to add the output to plot. What do we need to capture?

Student 2
Student 2

The Drain Current (ID) of the NMOS.

Teacher
Teacher

Fantastic! Today's summary: Log into the simulation, set up DC analysis, define sweep parameters, and do not forget to capture the output.

C-V Characteristics Simulation

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0:00
Teacher
Teacher

Now, we’ll focus on simulating C-V characteristics for NMOS transistors. First, why do we perform a C-V analysis?

Student 4
Student 4

To observe how the capacitance changes with varying gate voltages.

Teacher
Teacher

Exactly! Can anyone explain how we set up our AC analysis for this task?

Student 1
Student 1

We need to add an AC sweep and define our frequency and parameters.

Teacher
Teacher

Right! Remember, we sweep the gate voltage source while observing the total gate capacitance. What do we expect from the shape of the C-V curve?

Student 3
Student 3

It should reflect transitions between accumulation, depletion, and inversion regions.

Teacher
Teacher

Correct! Always document your findings. Summary for today: Set AC analysis for C-V, observe capacitance fluctuations, and understand the curve's significance.

Introduction & Overview

Read a summary of the section's main ideas. Choose from Basic, Medium, or Detailed.

Quick Overview

This section outlines the step-by-step procedures necessary for conducting laboratory experiments in VLSI design, including EDA tool usage and MOS transistor simulations.

Standard

The procedure section provides detailed experimental steps for setting up and conducting VLSI design lab experiments. It includes instructions for logging into the system, creating project directories, capturing schematics for NMOS and PMOS transistors, and simulating their IV and CV characteristics. Additionally, it highlights the importance of documenting observations and results throughout the lab work.

Detailed

Detailed Summary

This section, "Procedure/Experimental Steps," delineates the essential tasks for performing laboratory experiments in the VLSI Design Lab, particularly focusing on Electronic Design Automation (EDA) and MOS characteristics simulation. It consists of a clear sequence of steps grouped under specific tasks that guide students through successfully navigating and operating EDA tools.

Key Components of the Procedure:

  • Task 1: Introduction to EDA Environment and Project Setup: This first task includes logging into the workstation, creating a dedicated directory for the lab experiments, and launching the main EDA software.
  • Task 2: Schematic Capture of NMOS I-V/C-V Test Bench: Students learn to place NMOS transistors, voltage sources, and connect them to form a test bench for further simulations.
  • Task 3 & 4: Simulating NMOS I-V Characteristics: This involves launching the simulator, setting parameters for DC analysis, and extracting important metrics like threshold voltage from the ID-VGS curves.
  • Task 5: Simulating NMOS C-V Characteristics: Students apply AC analysis to measure capacitance and describe the influence of gate voltage changes on capacitance.
  • Task 6 & 7: PMOS transistor characteristics simulation: Similar to NMOS, students create schematics for PMOS and engage in comparative analysis of their electrical characteristics.
  • Detailed instructions for documenting all actions and observations throughout the lab exercises are also emphasized, ensuring comprehensive understanding and accurate reporting of results.

Audio Book

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Task 1: Introduction to the EDA Environment and Project Setup

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  1. Login to the Lab Workstation/Server:
  2. Power on the workstation or open your terminal/SSH client.
  3. Enter your provided username and password to log into the Linux environment.
  4. Navigate and Create Your Project Directory:
  5. Open a terminal window.
  6. Navigate to your home directory: cd ~
  7. Create a dedicated directory for this lab: mkdir -p vlsi_lab/lab1_mos_char
  8. Change into your new lab directory: cd vlsi_lab/lab1_mos_char
  9. Launch the Main EDA Design Environment:
  10. At the terminal, launch the primary design tool (e.g., for Cadence Virtuoso, type virtuoso & and press Enter). The & symbol runs the process in the background, keeping your terminal free.
  11. Familiarize yourself with the main design window, which typically includes menus, toolbars, and a design hierarchy browser.
  12. Create a New Library and Cell View:
  13. From the main EDA window, use the menu options (e.g., File > New > Library) to create a new library for your designs (e.g., mylib). Attach it to the appropriate technology file (provided by your instructor, e.g., gpdk_180nm or similar).
  14. Within your new library, create a new cell view for your NMOS test bench (e.g., File > New > Cell View, Library: mylib, Cell Name: nmos_iv_cv_tb, View: schematic). This will open the schematic editor.

Detailed Explanation

In this task, you begin by logging into the EDA environment, a software platform essential for designing electronic circuits. You first open the workstation and enter your login credentials. After logging in, you navigate to your home directory using terminal commands, which helps you stay organized. You then create a directory specifically for this lab to store your work, and launch the EDA design tool to begin your design tasks. Familiarizing yourself with the interface is crucial since it contains the tools you will be using for design. Finally, you create a library which is like a toolbox where your circuit designs will be stored, and within that library, you create a specific cell view where you'll design your NMOS test bench.

Examples & Analogies

Think of this task like setting up a new workspace in a workshop. When you start a new project, you unlock the door to the workshop (logging in), make sure everything is clean and organized (creating your project directory), and gather your tools and materials (launching the design tool and creating libraries). Just as you would familiarize yourself with the equipment you have available, in this case, you learn how to navigate the EDA environment which will help you efficiently complete your project.

Task 2: Schematic Capture of NMOS I-V/C-V Test Bench

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  1. Place NMOS Transistor:
  2. Locate the "Instance" placement tool (often an icon or from menu: Create > Instance).
  3. Browse the technology library (e.g., gpdk_180nm if using Cadence) to find the NMOS transistor (often named nmos or nfet).
  4. Place a single NMOS transistor on the schematic canvas.
  5. Set Parameters: Select the NMOS transistor. Modify its properties (often by pressing 'Q' or double-clicking). Set typical dimensions:
    • Width (W): e.g., 500n (500 nanometers) or 0.5u (0.5 micrometers)
    • Length (L): e.g., 180n (180 nanometers) or 0.18u (0.18 micrometers)
    • Number of fingers (if applicable): 1
    • Multiplier (if applicable): 1
  6. Place Voltage Sources:
  7. Place three independent DC voltage sources (vdc from analogLib or equivalent) for VGS, VDS, and VBS (Bulk voltage for NMOS).
  8. Place a Ground symbol (gnd from analogLib).
  9. Wire the Test Bench:
  10. Connect the Source terminal of the NMOS to a dedicated wire/net (e.g., "src").
  11. Connect the Drain terminal of the NMOS to a dedicated wire/net (e.g., "drn").
  12. Connect the Gate terminal of the NMOS to a dedicated wire/net (e.g., "gate").
  13. Connect the Bulk terminal of the NMOS directly to the Ground (gnd) symbol.
  14. Connect the positive terminal of one vdc to "gate" and its negative terminal to "src" (this is your VGS source).
  15. Connect the positive terminal of another vdc to "drn" and its negative terminal to "src" (this is your VDS source).
  16. Connect the third vdc to define the bulk voltage, connecting its positive terminal to "src" and negative to "bulk" (if not direct ground connection). For this lab, ensure bulk is at ground reference.
  17. Connect the gnd symbols from all voltage sources to a common ground net.
  18. Place output current probes if available (e.g., i_probe to measure ID from drain).
  19. Check and Save:
  20. Perform a "Check and Save" (often a toolbar button or Design > Check and Save) to ensure your schematic is electrically valid. Resolve any warnings or errors.

Detailed Explanation

In this task, you focus on creating the schematic for your NMOS test bench. First, you need to place an NMOS transistor using the EDA tools; this involves finding the component in the technology library and placing it on the schematic canvas. Once the NMOS is in place, you will set its parameters, including width and length, which define its physical attributes. After placing the NMOS, you add voltage sources that will supply the necessary voltages for gate, drain, and bulk connections. You will also wire these connections, ensuring that the NMOS transistor is correctly configured for simulation. Finally, you perform a check to validate the schematic—the equivalent of proofreading a blueprint to ensure everything is correctly drafted before proceeding.

Examples & Analogies

Imagine you are making a model of a circuit with building blocks. First, you pick the right block (the NMOS transistor) and measure it to ensure it fits your design (setting its parameters). Next, you would gather power sources (the voltage sources) to power your model and make the necessary connections to bring it all together. Before you call your model complete, you double-check (check and save) to make sure all the blocks are properly connected and there are no missing pieces.

Task 3: Simulating NMOS I-V Characteristics (ID-VDS)

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  1. Launch the Simulator:
  2. From the schematic window, launch the simulation environment (e.g., Launch > ADE L or similar).
  3. Select Analysis Type:
  4. Add a "DC Analysis" (Analyses > Choose Analyses... > dc).
  5. Set DC Sweep Parameters:
    • Select "Component Parameter" for the sweep variable.
    • Choose the VDS voltage source (e.g., VDS_source).
    • Set Start Value: 0V
    • Set Stop Value: VDD (e.g., 1.8V or 3.3V from technology file)
    • Set Step Type: Linear (or Automatic), Number of Steps: sufficient (e.g., 100 points).
    • Enable Parameter Sweep (for VGS): Go to the "Design Variables" or "Parametric Analysis" section.
    • Define VGS_val as a variable linked to your VGS source value.
    • Set VGS_val to sweep from 0V to VDD (e.g., 1.8V) with a step size (e.g., 0.2V or 0.4V).
  6. Select Outputs to Plot:
  7. In the schematic, select the Drain Current (ID) of the NMOS transistor (often by clicking on the drain terminal, or using a current probe).
  8. Ensure the output variable is added to the simulation's output list.
  9. Run Simulation:
  10. Start the simulation (e.g., "Netlist and Run" button).
  11. The waveform viewer will launch and display the ID-VDS curves.
  12. Analyze and Document:
  13. Observe the family of ID-VDS curves. Identify the cutoff, triode, and saturation regions for different VGS values.
  14. Capture a screenshot of your ID-VDS plots.

Detailed Explanation

In Task 3, you conduct simulations to explore the I-V characteristics of your NMOS transistor, specifically the relationship between the drain current (ID) and the drain-source voltage (VDS). You start by launching the simulation environment where you will configure your analysis settings. A DC analysis is conducted by sweeping the values of VDS while varying the gate-source voltage (VGS). You set specific parameters for the sweep, including the starting and stopping voltage levels. After configuring what outputs to plot—primarily the drain current—you run the simulation, resulting in a graphical representation of your results. Finally, you will interpret the plots to understand how the transistor behaves in different voltage regions.

Examples & Analogies

Think of this simulation like testing a new car model. First, you set up the track (launch the simulator), then determine how you want to test the car's performance (select the analysis type). You gradually increase the speed (DC sweep of VDS) while keeping an eye on performance indicators like fuel consumption (drain current). Once you track the data (run the simulation), you can evaluate the car's performance at various speeds to see how well it performs under different conditions.

Task 4: Simulating NMOS I-V Characteristics (ID-VGS) and Vt Extraction

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  1. Modify Simulation Setup:
  2. Return to the simulation environment. Keep the "DC Analysis" enabled.
  3. Change Sweep Parameter: Now, sweep the VGS voltage source (e.g., VGS_source) from 0V to VDD.
  4. Fix VDS: Set the VDS voltage source to a fixed value (e.g., VDD or a value sufficient to put the transistor into saturation).
  5. Ensure the output to plot is still ID of the NMOS.
  6. Run Simulation: Execute the simulation.
  7. Analyze and Extract Vt:
  8. Observe the ID-VGS curve.
  9. Method 1 (Visual Estimation): Visually estimate the VGS value where the drain current begins to significantly increase from zero.
  10. Method 2 (Linear Extrapolation - if supported by viewer): Many waveform viewers have tools to draw a tangent line to the steepest part of the ID-VGS curve and find its X-axis intercept, which gives a more precise Vt.
  11. Document the extracted threshold voltage.
  12. Capture a screenshot of your ID-VGS plot and indicate your Vt extraction method.

Detailed Explanation

This task delves deeper into the I-V characteristics of the NMOS transistor, focusing on the relationship between the drain current (ID) and gate-source voltage (VGS). You modify the simulation to sweep the VGS while fixing the VDS, effectively identifying the threshold voltage (Vt), which is crucial for understanding when the transistor turns on. After running the simulation, you analyze the ID-VGS curve, aiming to pinpoint the point at which the current begins to increase. You can do this visually or by using mathematical tools available in the simulation software. Extracting this threshold voltage provides essential insights for the design and functioning of circuits.

Examples & Analogies

Imagine you are testing a light switch. You gradually add voltage to the switch (sweep VGS) while monitoring when the light (drain current) begins to glow. At first, nothing happens (current at zero), then suddenly it lights up—this minimum voltage needed for the light to turn on is your threshold voltage (Vt). Just like finding this critical point helps you understand the light switch, determining Vt is essential for knowing at what point your transistor starts to function effectively.

Task 5: Simulating NMOS C-V Characteristics (Cgg vs. VGS)

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  1. Modify Test Bench (if needed for C-V setup):
  2. Ensure your NMOS schematic is set up for C-V measurement (some tools require specific AC sources or test configurations for capacitance extraction). Typically, you'll need to apply DC biases and then a small AC signal.
  3. Select Analysis Type:
  4. Add an "AC Analysis" (Analyses > Choose Analyses... > ac).
  5. Set AC Sweep Parameters:
    • Sweep Type: Frequency (e.g., single point at 1M Hz or 1k Hz, very low frequency for quasi-static C-V).
    • Sweep Range: Set start and stop frequencies (e.g., 1kHz to 1kHz for single point).
    • Enable Parameter Sweep (for VGS): Go to the "Design Variables" or "Parametric Analysis" section.
    • Sweep the VGS voltage source (e.g., VGS_source) from 0V to VDD (e.g., 1.8V).
  6. Select Outputs to Plot:
  7. Select the total gate capacitance (Cgg) of the NMOS transistor. The specific expression might be deriv(ID(MN0)) or a dedicated capacitance probe, depending on the tool.
  8. Run Simulation: Execute the simulation.
  9. Analyze and Document:
  10. Observe the Cgg vs. VGS curve.
  11. Explain the shape of the curve in terms of accumulation, depletion, and inversion regions.
  12. Capture a screenshot of your C-V plot.

Detailed Explanation

In this task, you aim to understand the capacitance-voltage (C-V) characteristics of your NMOS transistor by setting up for AC analysis. This involves ensuring your schematic is configured correctly; you apply DC biases and a small AC signal for the measurement. You then choose to conduct an AC analysis where frequency parameters can be set to observe the total gate capacitance (Cgg) relative to VGS. The results will lead to a C-V curve, which reflects how the capacitance varies based on the voltage applied. This is essential for understanding how the transistor will respond at different voltage levels, particularly in terms of switching speed and power consumption.

Examples & Analogies

Think of this task like checking the water level in a sponge as you apply pressure (voltage). The sponge's capacity to hold water changes with different pressures (voltages), just as the transistor's gate capacitance changes with VGS. By applying controlled bursts of pressure (AC signals), you observe how much water the sponge holds (gate capacitance at various gate voltages), helping you understand how effectively the transistor can switch in real-world applications.

Task 6: PMOS Transistor Characteristics Simulation

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  1. Create New Cell View for PMOS:
  2. Create a new schematic cell view for your PMOS test bench (e.g., pmos_iv_cv_tb).
  3. Schematic Capture for PMOS:
  4. Place a single PMOS transistor (pmos or pfet).
  5. Set Parameters: Use similar W/L dimensions as the NMOS (e.g., W=0.5u, L=0.18u). Note: For later inverter design, PMOS W is often larger than NMOS W.
  6. Place three independent DC voltage sources for VGS, VDS.
  7. Connect the Bulk terminal of the PMOS to the highest potential (VDD) symbol.
  8. Wire the test bench appropriately, similar to the NMOS, but keeping in mind PMOS operates with negative VGS/VDS relative to VDD for current flow.
    • Example: Source to VDD_source, Gate to VGS_source, Drain to VDS_source. The VGS_source and VDS_source will typically be swept from VDD downwards to 0V.
  9. Simulate PMOS I-V Characteristics (ID-VDS and ID-VGS):
  10. Repeat steps 4.3 and 4.4 for the PMOS transistor. Remember that PMOS current flows when VGS is below Vt (negative Vt, or VGS closer to 0V than VDD).
  11. Observe and document the differences in curve shapes and operating regions compared to the NMOS.
  12. Extract the threshold voltage (Vt) for the PMOS transistor (it will be a negative value or close to 0V relative to VDD).
  13. Capture screenshots of your PMOS I-V plots.
  14. Simulate PMOS C-V Characteristics (Cgg vs. VGS):
  15. Repeat step 4.5 for the PMOS transistor.
  16. Observe and document the C-V curve, noting how it differs from NMOS due to opposite carrier types and voltage dependencies.
  17. Capture a screenshot of your PMOS C-V plot.

Detailed Explanation

In Task 6, you transition to working with PMOS transistors. First, you create a new cell specifically for your PMOS test bench. Similar to the NMOS setup, you place the PMOS transistor in the schematic and configure its parameters according to your design goals. You need to remember that PMOS devices operate under slightly different conditions, primarily with negative gate-source voltages. After configuring the test bench, you simulate the I-V characteristics for the PMOS, similar to the NMOS but observing that the current behavior and voltage thresholds reflect the opposite charge carriers used in PMOS technology. You also measure capacitance characteristics, noting the differences from NMOS based on the unique properties of PMOS transistors.

Examples & Analogies

Switching to PMOS is like changing from driving a gasoline car to an electric car. The principles are still the same (you still need to know how to steer and accelerate), but the specifics of how you operate are different—like fueling with electricity instead of gas. Just as electric cars might require different types of charging stations and power connections, PMOS transistors have their own operating conditions and characteristics that you need to understand when designing circuits.

Task 7: Impact of W/L Ratio (Comparative Analysis)

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  1. Create New Schematic (e.g., nmos_wl_impact_tb):
  2. Copy your nmos_iv_cv_tb schematic into a new cell view.
  3. Parametric Simulation Setup:
  4. Modify the NMOS transistor instance. Instead of a fixed W, define a design variable (e.g., my_W) for its width.
  5. In the simulation environment, set up a "Parametric Analysis" to sweep my_W through several values (e.g., 0.5u, 1u, 2u).
  6. Run the ID-VDS or ID-VGS simulation with this parametric sweep.
  7. Analyze and Document:
  8. Observe how the ID current changes dramatically with varying W.
  9. Observe how the Cgg capacitance changes with varying W.
  10. Quantify the change in current drive as W is doubled.
  11. Capture screenshots showing the family of curves for different W values.

Detailed Explanation

In Task 7, you focus on understanding how varying the width-to-length (W/L) ratio of your NMOS transistor impacts its performance. You duplicate your existing NMOS schematic to keep a base case for comparisons. By modifying the width as a variable, you can conduct parametric simulations to track how different widths affect the ID current and gate capacitance (Cgg). The importance of this analysis lies in the ability to quantify how increasing width enhances current drive capabilities, ultimately impacting the transistor's performance in design scenarios. By capturing screenshots of the results, you can visually document the relationship between design parameters and actual transistor behavior.

Examples & Analogies

This task can be likened to testing the impact of different tire widths on the performance of a race car. A wider tire (larger W) allows for better traction and faster speeds but may require more energy (increased power consumption and capacitance). In racing, engineers must balance tire size with efficiency and speed, just as you analyze how changing the W/L ratio affects the NMOS transistor's performance to achieve optimal circuit design.

Definitions & Key Concepts

Learn essential terms and foundational ideas that form the basis of the topic.

Key Concepts

  • Schematic Capture: The process of designing circuits using graphical tools.

  • Simulation: A crucial step for predicting circuit behavior before physical implementation.

  • DC Analysis: A method to analyze steady-state circuit responses.

  • Transistor Characteristics: Understanding how NMOS and PMOS function is vital for design.

Examples & Real-Life Applications

See how the concepts apply in real-world scenarios to understand their practical implications.

Examples

  • An example of a simple NMOS circuit might involve simulating a basic switching circuit with different gate voltages to analyze its ID-VGS characteristics.

  • In a C-V analysis, students may apply varying gate voltages to an NMOS transistor to observe how the gate capacitance influences switching speed.

Memory Aids

Use mnemonics, acronyms, or visual cues to help remember key information more easily.

🎵 Rhymes Time

  • For every NMOS, a boost in volt gives current flow, that's how we know!

📖 Fascinating Stories

  • Imagine builders using blueprints (EDA) to construct a house (circuit); without it, there’d be chaos in wiring!

🧠 Other Memory Gems

  • To remember the steps for schematic capture: ‘P-L-W’ - Place, Label, Wire.

🎯 Super Acronyms

C-V stands for ‘Capacitance-Voltage’ - think of ‘Current Variable’ for dynamic understanding.

Flash Cards

Review key concepts with flashcards.

Glossary of Terms

Review the Definitions for terms.

  • Term: EDA Tools

    Definition:

    Electronic Design Automation tools used for designing and simulating electronic systems.

  • Term: NMOS Transistor

    Definition:

    N-channel Metal Oxide Semiconductor transistor used in digital circuits.

  • Term: PMOS Transistor

    Definition:

    P-channel Metal Oxide Semiconductor transistor, generally used along with NMOS in CMOS technology.

  • Term: IV Characteristics

    Definition:

    Current-Voltage characteristics which describe how the current through a device varies with the voltage across it.

  • Term: CV Characteristics

    Definition:

    Capacitance-Voltage characteristics indicating how capacitance varies with applied voltages.

  • Term: Threshold Voltage (Vt)

    Definition:

    The minimum gate-to-source voltage that is needed to create a conducting path between the source and drain terminals.

  • Term: Schematic Capture

    Definition:

    The process of creating electronic schematics using graphical symbols to represent components.