For this lab, you are assumed to have successfully completed the schematic design (Lab 2) and the physical layout design (e.g., Lab 4, ensuring it's DRC-clean) of a CMOS inverter. If you have not, use a provided, DRC-clean CMOS inverter layout.

1. Open Layout View: Launch your circuit design environment (e.g., Cadence Virtuoso) and open the layout view of your CMOS inverter. Ensure it is the top-level view or the cell that you intend to extract.
2. Launch Extraction Tool: Navigate to the specific menu or command to initiate the parasitic extraction. This is often found under a 'Verification' or 'Tools' menu (e.g., Calibre -> Run PEX, Assura -> RCX, QRC -> Run).
3. Configure Detailed Extraction Settings:
4. Extraction Scope: Confirm that you are extracting from the current cell view.
5. Output Netlist Format: Select a common simulation-ready format, typically SPICE or Spectre (often selected by default). This netlist will include the extracted R and C components.
6. Extraction Type: Choose 'RC' extraction. This ensures that both resistive and capacitive parasitics are calculated. Avoid 'C only' or 'R only' unless specifically instructed for specialized analysis.
7. Transistor Models: Verify that the correct technology file and model libraries are linked. The extraction tool needs this to correctly characterize the intrinsic device parasitics (e.g., gate capacitance).
8. Substrate Connection: Ensure the substrate/bulk connection is accurately defined for extraction. Typically, the substrate is considered grounded or tied to VDD/GND as per design rules. This affects how substrate capacitances are modeled.
9. Output File Naming: Specify a clear name for your extracted netlist (e.g., inverter_pex.spi or inverter_qrc.scs).
10. Flat vs. Hierarchical Extraction (for larger designs): For this single inverter, a flat extraction is sufficient. Understand that for complex designs, hierarchical extraction can be more efficient.
11. Run Extraction: Execute the extraction process. This may take a few moments depending on the complexity of the layout and the tool's settings. Monitor the tool's log window for any warnings or errors during extraction.
12. Examine Extracted Netlist (Crucial Step for Understanding):
13. Navigate to the directory where the extracted netlist file was saved.
14. Open the generated .spi or .scs file using a text editor.
15. Analyze the Contents:
    • Identify the original transistors (nMOS, pMOS) and their connections.
    • Observe the newly added parasitic elements:
    • Look for capacitor instances (e.g., C1, C_int_VOUT) connected to various nodes. Note their values (e.g., in fF).
    • Look for resistor instances (e.g., R1, R_VOUT_TRACE) in series with interconnects or at contacts/vias. Note their values (e.g., in Ohms).
    • Pay particular attention to the output node (Vout) and input node (Vin) and identify the parasitic capacitances loading these nodes.
    • Note how the tool assigns unique names to each parasitic element.

1. Launch LVS Tool: From your design environment, open the LVS verification tool (e.g., Calibre -> Run LVS, Assura -> LVS, PVS -> LVS).
2. Specify Input Files for Comparison:
3. Layout Input: Point to the top-level cell view of your inverter layout.
4. Schematic Input: Point to the top-level cell view of your inverter schematic.
5. LVS Rule Deck/Technology File: Load the specific LVS rule deck (.lvs file) provided by your technology foundry. This file contains the rules for device recognition (how to identify a transistor from layout layers) and connectivity comparison.
6. Configure LVS Options (Detailed):
7. Comparison Mode: Ensure the tool is set to perform a full device and net comparison.
8. Power/Ground Recognition: Explicitly define the names of your power (VDD) and ground (GND) nets. Many tools allow you to specify these as 'power' or 'ground' nets to avoid unnecessary mismatch reports related to power distribution.
9. Ignore Parameters/Nets: For this basic lab, avoid ignoring any parameters or nets. For complex designs, selective ignoring might be used for specific debug scenarios.
10. Connectivity Extraction: Verify that the tool is set to extract connectivity from both the layout and schematic.
11. Run LVS: Execute the LVS comparison. This process involves the tool extracting a netlist from the layout internally (if not already done) and comparing it against the schematic netlist.
12. In-depth Analysis of the LVS Report (Critical Debugging Skill):
13. Locate and open the LVS report file (e.g., lvs.report, _LVS.rpt).
14. Successful LVS (Ideal Case): If LVS passes, the report will display a clear message indicating 'Layout and Schematic Match,' 'Netlists are Equivalent,' or 'LVS Clean.' It will also typically summarize the number of devices and nets found in both.
15. LVS Mismatches (Common Scenarios & Debugging):
    • 'Mismatch in Number of Devices': Means you have more or fewer transistors in one view than the other. Check for accidental deletion, extra instantiation, or incorrect device recognition in layout.
    • 'Device Type Mismatch': An nMOS in schematic recognized as a pMOS in layout, or vice-versa. Check layer definitions in layout.
    • 'Parameter Mismatch (W/L)': The W/L of a transistor in layout doesn't match the schematic. Double-check your layout dimensions.
    • 'Net Mismatches': This is the most common and detailed category.
    • 'Open Circuits': A net in the schematic is not fully connected in the layout. Visually inspect the routing.
    • 'Short Circuits': Two distinct nets in the schematic are physically connected in the layout. This is severe. Use the LVS results viewer (if available) to highlight the shorted nets.
    • 'Missing Nets/Extra Nets': A net exists in one view but not the other, or is improperly recognized.
    • 'Pin Mismatch/Swap': Input/output pins or internal device terminals are connected to the wrong places.
    • Debugging Strategy:
    • Use the LVS report to pinpoint the exact nature and location of the error.
    • Utilize the LVS results viewer (if your tool provides one), which graphically highlights mismatches directly on the layout.
    • Systematically re-check connections in both schematic and layout for the reported errors.
    • Correct the errors in your layout, save, and re-run LVS until a clean report is obtained. This iterative process is fundamental to physical design.

1. Create/Modify Simulation Testbench:
2. Open the schematic of your inverter testbench.
3. Crucial Step: Instead of placing the schematic symbol of your inverter, you will now instantiate its extracted view. In most tools, you can right-click on the inverter instance and select 'View' or 'Reference' to choose 'extracted' or 'pex' view. This tells the simulator to use the netlist with parasitics for this instance.
4. Ensure your input stimulus (Vin pulse source) and output probes (Vout measurement) are configured identically to your pre-layout transient simulation setup from Lab 2.
5. Set the transient simulation stop time to observe multiple switching cycles (e.g., 5-10 times the expected gate delay).
6. Run Post-Layout Simulation: Execute the transient simulation using the extracted view.
7. Plot Waveforms: Display the Vin and Vout waveforms on the waveform viewer.

1. Retrieve Pre-layout Simulation Results: Load the Vin and Vout waveforms from your previous pre-layout transient simulation (from Lab 2). Ensure the input stimulus is identical.
2. Overlay and Visual Comparison:
3. On a single plot, display the following waveforms:
   • Input waveform (Vin).
   • Pre-layout output waveform (Vout_pre).
   • Post-layout output waveform (Vout_post).
4. Carefully observe the differences in the rise and fall times, and particularly the shift in the switching points (delays).
5. Precise Delay Measurements:
6. Using the measurement tools (e.g., cursors, built-in delay functions) of your waveform viewer:
   • Propagation Delay Low-to-High (t_PLH): Measure the time difference from 50% of Vin (rising edge) to 50% of Vout (falling edge).
   • Propagation Delay High-to-Low (t_PHL): Measure the time difference from 50% of Vin (falling edge) to 50% of Vout (rising edge).
   • Average Propagation Delay (t_PD): Calculate (t_PLH + t_PHL) / 2.
7. Perform these measurements for both the pre-layout and post-layout Vout waveforms.
8. Detailed Power Dissipation Analysis (Post-Layout):
9. Dynamic Power Calculation:
   • Measure the instantaneous current flowing from the VDD supply (I(VDD)) during the simulation.
   • Calculate instantaneous power: P_inst = VDD * I(VDD).
   • Use the waveform calculator to compute the average power over several stable switching cycles (e.g., from the start of the second cycle to the end of the second-to-last cycle to avoid transient effects).
   • If you have calculated pre-layout power (or estimated it using the formula 0.5 * C_load * VDD^2 * f), make a direct comparison.
10. Observation/Results:
11. Document all your findings in a clear, highly organized, and professional manner, using tables, plots, and screenshots as indicated.