Important Tip: Always save your work as you go! Make sure your graphs and pictures are clearly labeled with titles and what the lines mean.

1. Goal: See how a digital circuit is written in a Hardware Description Language (HDL) for the computer to understand.
2. Steps:
3. Get the Code: Your teacher will give you a Verilog (or VHDL) code file for a simple digital circuit. It might be something like:
4. A simple 4-bit addition circuit.
5. A basic counting circuit.
6. A simple "state machine" (a circuit that remembers a few different modes).
7. Look at the Code: Open this code file in your text editor.
8. Find where the main circuit block starts (like module in Verilog).
9. See where the inputs, outputs, and internal signals are listed.
10. If it's a calculating circuit, find how it describes adding or other operations.
11. If it's a memory circuit (like a counter), find how it uses clock signals to store information.
12. Think About It: Imagine how this written description will turn into actual basic gates.
13. What to Write in Your Report:
14. Briefly explain what the provided code does (e.g., "This code describes a 4-bit counter.").
15. Explain why this code is "synthesizable" – meaning a computer can automatically turn it into physical gates.

1. Goal: Learn how special software automatically converts your high-level design code into a detailed blueprint of basic gates.
2. Steps:
3. How it Works (If no software access): Your teacher will explain the conceptual steps of how the "synthesis tool" works:
4. Reads Your Code: It takes your Verilog/VHDL design.
5. Applies Rules: You give it rules, like "this circuit needs to run at 100 MHz" or "keep the circuit small."
6. Loads Gate Library: It looks at a special library file that lists all the available basic gates (AND, OR, flip-flops, etc.) and their characteristics (how fast they are, how much power they use).
7. Optimizes & Maps: It figures out the best way to build your circuit using these gates, making it as fast or small as possible based on your rules.
8. Creates Gate Blueprint: It generates a new file, the "gate-level netlist," which is the detailed list of gates and their connections.
9. Using the Software (If you have access):
10. Start the Program: Open your synthesis software (e.g., Synopsys Design Compiler).
11. Load Gates: Tell the program where your standard cell library files are.
12. Load Your Design: Load your Verilog/VHDL code into the program.
13. Set Rules: Tell the program about your clock speed and any other timing requirements. Your teacher will give you specific commands for this.
14. Run Synthesis: Give the command to "compile" or "synthesize" your design. This is where the magic happens!
15. Save the Blueprint: Save the new file that contains the gate-level netlist (usually a .v or .vg file).
16. Initial Summary: Look for a summary report from the synthesis tool. It usually tells you how many gates were used and the estimated size (area) of your circuit.
17. What to Write in Your Report:
18. Describe the main steps involved in synthesis, either from your experience with the software or from your teacher's explanation.
19. Write down the total number of basic gates and the estimated area that the tool reported for your circuit.

1. Goal: Learn to read and understand the detailed list of basic gates that your design code became.
2. Steps:
3. Open the File: Open the newly generated gate-level netlist file in your text editor.
4. Examine the Structure:
5. Find the main block of your circuit in this file.
6. You'll see lines that represent individual basic gates (like INV for inverter, NAND2X1 for a 2-input NAND gate). Each line will be an "instance" of a gate from the library.
7. Gate Instances: Notice the name of the gate (e.g., INV), a unique name for that specific copy of the gate (e.g., U1), and then connections to its inputs and outputs.
8. See how the original signals from your design code (inputs, outputs) are now connected to the inputs and outputs of these basic gates.
9. If your design had memory (flip-flops), find those instances (e.g., DFF_X1).
10. Match Code to Gates: Try to mentally follow a simple path in this gate list and connect it back to a line or a block of logic in your original design code. For example, if you designed an adder, see if you can spot the gates that make up one of the adder stages.
11. What to Write in Your Report:
12. Include a small piece (like 5-10 lines) of your gate-level netlist in your report.
13. Explain what each part of that snippet means (the gate type, its unique name, and what signals are connected to its inputs and outputs).
14. Discuss how this gate-level netlist is different from your original design code (e.g., it's a detailed list of physical parts, not just a description of behavior).

1. Goal: Understand the main ideas behind STA, which is how we automatically check if our chip will run fast enough.
2. Steps (Mostly concepts, using examples from your teacher):
3. Why STA is Needed: Think about why just simulating your circuit is not enough for huge chips (it's too slow to test every possible way data can move). STA mathematically checks all paths, which is much faster.
4. Circuit Paths: Understand the different ways data can travel through your circuit:
5. From Input to Flip-Flop: Data comes from outside the chip to a flip-flop.
6. From Flip-Flop to Flip-Flop: Data moves from one flip-flop to another.
7. From Flip-Flop to Output: Data goes from a flip-flop out of the chip.
8. From Input to Output: Data goes directly from an input to an output, only through basic gates (no flip-flops).
9. Clock Speed Rule: The most important rule is the clock period (Tclk) – how fast your clock "ticks."
10. Setup Time Explained:
11. What it means: Data needs to be stable and "set up" at the input of a flip-flop before the clock edge arrives.
12. Problem: If data arrives too late, it's a "setup violation." The flip-flop might not store the correct value.
13. The Check: The time it takes for data to arrive must be less than the clock period minus the setup time needed by the flip-flop.
14. Hold Time Explained:
15. What it means: Data needs to "hold" stable at the input of a flip-flop after the clock edge arrives.
16. Problem: If data changes too quickly (arrives too early), it's a "hold violation." The flip-flop might also get confused.
17. The Check: The time it takes for data to arrive must be greater than the hold time needed by the flip-flop.
18. The Slowest Path (Critical Path):
19. STA finds the "longest" or slowest path in your circuit. This path determines the absolute fastest clock speed your circuit can handle. This is called the critical path (for setup time).
20. STA also finds the "shortest" or fastest path, which is important for hold time.
21. "Slack" (Room to Breathe): Slack is simply the difference between when data needs to be there and when it actually gets there.
22. Positive Slack: Good! Your timing rules are met, you have extra time.
23. Negative Slack: Bad! Your timing rules are broken, data is either too late or too early.
24. What to Write in Your Report:
25. In your own words, explain what "setup time" and "hold time" are for a flip-flop.
26. Describe what a "critical path" is and why finding it is so important for chip performance.
27. Explain "slack" – what does positive slack mean, and what does negative slack mean?

1. Goal: Learn how to look at a report from an STA tool and find the important numbers about circuit speed.
2. Steps (Mostly by looking at reports provided by your teacher):
3. Get the Report: Your teacher will give you a simplified STA report (or parts of one) for your synthesized design.
4. Scan the Report: Look for sections like:
5. Design Info: Your circuit's name, the basic gate library used.
6. Clock Info: Details about your clock signal.
7. Summary: A quick overview of the worst timing issues (the biggest negative slack).
8. Detailed Path Reports: This is the most important part! It shows you step-by-step information for specific paths.
9. Focus on a Critical Path: Find a detailed report for a "critical path" (the one with the worst slack).
10. Starting Point: Where the data path begins (e.g., an input pin or a flip-flop's output).
11. Ending Point: Where the data path ends (e.g., a flip-flop's input or an output pin).
12. Clock Delay: How long it takes the clock signal to reach the endpoint's clock pin.
13. Data Delay: How long it takes the data to travel through all the gates and wires from the starting point to the ending point.
14. Time Needed (Required Time): The latest the data should arrive at the endpoint to meet the timing rule.
15. Time Arrived (Arrival Time): The actual time the data does arrive at the endpoint.
16. Slack: The difference between "Time Needed" and "Time Arrived."
17. Gate List: See the list of individual gates and wires along this critical path, and their individual delays.
18. What to Write in Your Report:
19. Briefly describe the main parts of an STA report.
20. Show a small piece (or draw a simple diagram) of a critical path you found in the report.
21. For your critical path, clearly list its: Starting Point, Ending Point, Clock Delay, Data Delay, Time Needed, Time Arrived, and Slack.
22. Tell us if the timing rule (setup) was met (positive slack) or broken (negative slack). Explain what that means for your circuit's speed.
23. Explain how looking at this report helps chip designers find and fix slow parts of their circuit.