4.7.1 What is Logic Synthesis?

• Definition: Logic synthesis is the automated process of translating a high-level HDL description (like Verilog) of a digital circuit into an optimized, technology-specific gate-level netlist.
• Netlist: A netlist is a description of the circuit in terms of basic logic gates (AND, OR, NOT, flip-flops) and their interconnections, typically provided by a "standard cell library" for ASICs or specific "logic elements" (like Lookup Tables and Flip-flops) for FPGAs.
• Goals of Synthesis:
• Functionality: Ensure the synthesized netlist implements the exact logical behavior described in the HDL code.
• Optimization: Minimize area (number of gates), maximize speed (meet timing constraints, reduce critical path), and minimize power consumption, based on user-defined constraints.
• Technology Mapping: Map the optimized logic onto the specific gates available in the chosen target technology library.

4.7.2 Synthesizable vs. Non-Synthesizable Constructs

Not all Verilog constructs describe physical hardware. Some are purely for simulation and will be ignored or cause errors during synthesis.

• Synthesizable Constructs (Hardware Realizable): These describe structures that can be built using physical gates and wires.
• module declarations, input, output, inout ports.
• wire, reg (when used appropriately to infer combinational or sequential logic).
• assign statements (for combinational logic).
• always @(*) for combinational logic (ensuring no implied latches).
• always @(posedge clk) or always @(negedge clk) for sequential logic (flip-flops, registers).
• if-else, case statements (when fully specified to avoid latches).
• Arithmetic, logical, bitwise, relational, reduction, shift, concatenation, conditional operators.
• parameter (defines constants).
• for loops with fixed, calculable bounds (synthesizer "unrolls" them into combinational logic).
• Non-Synthesizable Constructs (Simulation-Only): These describe testbench behavior, timing, or high-level abstract concepts that don't have direct hardware equivalents.
• initial blocks.
• Timing control (#delay).
• System tasks ($display, $monitor, $finish, $time, file I/O).
• real, realtime data types.
• force, release statements (for overriding signals in simulation).
• forever, while, repeat loops without fixed bounds (synthesizer cannot unroll them).
• Recursive functions/tasks.
• specify blocks (for timing specification).

4.7.3 Common Synthesis Issues

• Implied Latches: As discussed in Module 4.5, if a reg variable in an always @(*) block is not assigned a value under all possible input conditions, the synthesizer will infer a latch to hold its value. Latches can lead to race conditions and are harder to analyze for timing, making them generally undesirable in synchronous designs.
• Solution: Always provide a default assignment or ensure all conditional paths are covered (else for if, default for case).
• Combinational Loops: Occur when a signal's value depends on itself through a purely combinational path, creating an oscillation or undefined state.
• Example: assign A = B & C; assign C = A | D; (creates a loop: A -> C -> A).
• Problem: Such loops are unstable and problematic in hardware.
• Solution: Avoid direct combinational feedback loops. If feedback is necessary, it must go through a sequential element (flip-flop) to break the loop and synchronize it to a clock.
• Over-constrained or Under-constrained Designs: If timing constraints are too tight, synthesis might fail. If too loose, the resulting hardware might be slower than necessary.
• Unintended Logic Sharing: Synthesizers try to optimize. If not careful, distinct parts of your logic might get unintentionally merged.
• Poorly Written RTL (Register Transfer Level) Code: Ambiguous or inefficient Verilog code can lead to sub-optimal synthesis results (larger area, slower speed). Clear, concise, and structured RTL coding style is critical.

4.7.4 Mapping to Target Technology:

• ASIC (Application-Specific Integrated Circuit): Synthesizers map your design onto standard cells from a specific foundry's library. These are pre-designed and characterized basic gates (AND, OR, NOT), flip-flops, adders, etc., with known area, delay, and power characteristics.
• FPGA (Field-Programmable Gate Array): Synthesizers map your design onto the FPGA's programmable logic blocks, typically consisting of Look-Up Tables (LUTs) (which can implement any Boolean function), flip-flops, and dedicated logic like adders or multipliers. The physical interconnections are configured electronically.