4.6.1 Purpose of Testbenches:

• Verification: The primary goal is to verify that the "Design Under Test" (DUT) behaves as expected under various input conditions.
• Stimulus Generation: Apply input signals (stimuli) to the DUT over time.
• Output Monitoring: Observe and capture the outputs of the DUT.
• Self-Checking: Optionally compare DUT outputs against expected values to automate verification.
• Debugging: Provide waveforms and messages to help debug design flaws.
• No Synthesis: Testbenches are purely for simulation and are never synthesized into hardware. Therefore, they can use non-synthesizable constructs (e.g., # delays, initial blocks, file I/O).

4.6.2 Structure of a Basic Testbench:

A testbench is typically a top-level Verilog module with no inputs or outputs. It instantiates the DUT and generates the necessary input waveforms.

module my_design_tb; // No ports for a testbench
// 1. Declare signals (wires/regs) for connecting to the DUT's ports
// These signals act as the inputs/outputs to your DUT
reg clk;
reg reset_n;
reg [7:0] data_in_A;
reg [7:0] data_in_B;
wire [7:0] gcd_result_out;
wire done_flag;

// 2. Instantiate the Design Under Test (DUT)
// Connect the testbench signals to the DUT's ports
GCD_Processor DUT (
.A_in(data_in_A),
.B_in(data_in_B),
.clk(clk),
.reset_n(reset_n),
.result_out(gcd_result_out),
.done_flag(done_flag)
);

// 3. Clock Generation (using an always block with forever)
parameter CLK_PERIOD = 10; // 10 ns clock period (5 ns high, 5 ns low)
initial begin
clk = 1'b0; // Initial clock value
forever #(CLK_PERIOD / 2) clk = ~clk; // Toggle clock every half period
end

// 4. Initial Block for Stimulus Application and Reset Generation
initial begin
// Apply reset (active low)
reset_n = 1'b0;
data_in_A = 8'b0;
data_in_B = 8'b0;
#(CLK_PERIOD * 2); // Hold reset for 2 clock cycles
reset_n = 1'b1; // Release reset
// Apply stimuli for GCD(48, 18) = 6
data_in_A = 8'd48;
data_in_B = 8'd18;
#(CLK_PERIOD * 1); // Wait for one clock cycle for inputs to register
// Wait for the done flag, or a maximum time
wait(done_flag);
$display("GCD(48, 18) = %0d, Expected: 6", gcd_result_out); // Display result
// Apply new stimuli for GCD(100, 75) = 25
data_in_A = 8'd100;
data_in_B = 8'd75;
#(CLK_PERIOD * 1); // Wait
wait(done_flag);
$display("GCD(100, 75) = %0d, Expected: 25", gcd_result_out);
#(CLK_PERIOD * 5); // Allow some time for final signals to settle
$finish; // End simulation
end
// 5. Monitoring Outputs (using system tasks)
initial begin
$display("Time\\tClock\\tReset\\tA_in\\tB_in\\tGCD_Result\\tDone");
$monitor("%0t\\t%b\\t%b\\t%0d\\t%0d\\t%0d\\t\\t%b", $time, clk, reset_n, data_in_A,
data_in_B, gcd_result_out, done_flag);
end
endmodule

4.6.3 System Tasks for Simulation:

• $display("format_string", arg1, ...);: Prints messages to the console during simulation. Behaves like printf in C.
• $monitor("format_string", arg1, ...);: Prints messages to the console whenever any of its arguments change value. Useful for continuously tracking signals. Only one $monitor can be active at a time.
• $strobe("format_string", arg1, ...);: Similar to $display, but prints values at the very end of the current simulation time step, after all values have stabilized. Useful for seeing final results for a given time step.
• $time: Returns the current simulation time.
• $finish;: Terminates the simulation.
• $stop;: Halts the simulation, allowing interaction (e.g., examining waveforms).
• $dumpfile("filename.vcd");, $dumpvars(0, testbench_instance);: Used to create a Value Change Dump (VCD) file for waveform viewing in a waveform viewer.

4.6.4 Self-Checking Testbenches (Briefly):

More advanced testbenches include logic to automatically check if the DUT's outputs match expected values, reporting "PASS" or "FAIL".

// Example within initial block after getting result
if (gcd_result_out == 8'd6) begin
$display("TEST PASSED for GCD(48, 18)");
end else begin
$display("TEST FAILED for GCD(48, 18): Got %0d, Expected 6", gcd_result_out);
end