At its most basic level, memory is conceptualized as a vast array of storage cells, each capable of holding a single bit of information. These bits are then grouped into larger, more manageable units.

Byte-addressable Memory:

This is the overwhelmingly dominant memory organization in modern microcomputer systems. In a byte-addressable system, the smallest unit of memory that can be uniquely identified and accessed by a distinct address is a byte (8 bits). This means if you have a memory chip with 1024 bytes, it will have addresses from 0 to 1023, where each address corresponds to one byte.

Example: If memory location 0010textH contains the byte A5textH, and location 0011textH contains 3CtextH, these are two distinct, individually addressable bytes.

Word-addressable Memory:

In some older or specialized architectures, memory might be organized in "words," where a word is typically the native data size of the CPU (e.g., 16 bits, 32 bits). In a word-addressable system, each unique address refers to an entire word, not an individual byte.

Example: If a system is 16-bit word-addressable, and address 0000textH contains the word 1234textH, then the byte 12textH would be at the higher byte address within that word, and 34textH at the lower byte address.

The CPU initiates all memory access operations. To perform a read or write, the CPU places the binary address of the desired memory location onto the address bus. Concurrently, it asserts the appropriate control signals (e.g., READ or WRITE) on the control bus. The memory controller or decoding logic then interprets this address to select the correct memory chip and the specific location within that chip.

Maximum Addressable Memory:

As discussed in Section 1.2.1, the number of address lines determines the maximum addressable memory. For an N-bit address bus, the total number of distinct memory locations is 2^N.

Calculation Example: Consider a microcontroller with a 20-bit address bus. Maximum addressable memory = 2^20 bytes. 2^20 = (2^10) * (2^10) = 1024 * 1024 = 1,048,576 bytes. This is exactly 1textMB (Megabyte). So, a 20-bit address bus can directly address 1 Megabyte of memory.

Memory Decoding:

When multiple memory chips (or other addressable devices) are connected to the same address bus, a mechanism is needed to ensure that only the intended chip responds to a given address. This mechanism is called memory decoding. Decoding logic (often implemented using logic gates like AND, OR, NOT, or specialized decoder ICs) takes certain bits from the address bus as input and generates a chip-select signal for each memory chip. Only the chip whose signal is active will enable its data bus drivers and respond to the CPU's request.

A memory map is a logical representation or diagram that illustrates how the entire address space of a microcomputer system is allocated and partitioned among various memory devices (RAM, ROM) and I/O devices (if memory-mapped). It is a crucial design document for both hardware engineers (for interconnection) and software developers (for knowing where to place code and data, and how to access peripherals).

Key Aspects of a Memory Map:

• Address Ranges: Specifies the starting and ending physical addresses for each component.
• Component Type: Identifies what device occupies a particular address range (e.g., ROM, SRAM, specific I/O controller).
• Read/Write Permissions: Indicates whether a memory region is readable, writable, or executable.
• Gaps: Often, there are unassigned "gaps" in the address space. Accessing these unassigned addresses typically results in a bus error or no response.

Example Memory Map (Simplified 8-bit Microcontroller with 16-bit Address Bus):

Total Address Space: 0000textH to FFFFtextH (64 KB)