An interrupt is a hardware or software-generated event that causes the CPU to temporarily suspend its current normal program execution, save its current context, and then immediately transfer control to a special segment of code designed to handle that specific event. Once the event is handled, the CPU restores its saved context and resumes execution of the interrupted program from where it left off. This mechanism allows the CPU to efficiently respond to asynchronous events without constantly checking for them.

Interrupts can be broadly categorized based on their source and characteristics:

• Hardware Interrupts: Generated by external or internal hardware devices.
• Maskable Interrupts (IRQ): These interrupts can be enabled or disabled (masked) by software. The CPU has a dedicated Interrupt Enable (IE) register or status bits that control whether it will acknowledge these interrupts. They are used for most peripheral devices.
  • Examples: Keyboard press, mouse movement, data ready at a serial port, timer overflow, external pin change.
• Non-Maskable Interrupts (NMI): These interrupts have the highest priority and cannot be disabled by software. They are typically reserved for critical system events that require immediate attention and cannot be ignored.
  • Examples: Power failure warning, memory parity error, watchdog timer expiration (indicating a software lock-up).
• Software Interrupts (Traps/Exceptions): Generated by software instructions or by exceptional conditions arising during program execution.
• System Calls: Explicit software instructions (e.g., INT instruction in 8086) used to request services from the operating system (e.g., file I/O, memory allocation).
• Exceptions/Faults: Occur due to an abnormal condition during instruction execution. These are often unplanned and indicate an error.
  • Examples: Division by zero, illegal instruction opcode, memory access violation (accessing protected memory).

When an interrupt occurs, the CPU follows a specific sequence of steps to handle it:

1. Current Instruction Completion: The CPU typically completes the execution of the instruction it is currently processing.
2. Interrupt Request Acknowledgment: The CPU acknowledges the interrupt, assuming it is enabled (for maskable interrupts).
3. Context Saving (PUSHing Registers): The CPU automatically (or through initial ISR code) saves the critical state of the currently executing program. This includes:
4. The current value of the Program Counter (PC), so the CPU knows where to return after handling the interrupt.
5. The contents of the Status/Flag Register, which reflects the CPU's state (e.g., carry, zero flags).
6. Often, the contents of other critical registers (e.g., accumulator, general-purpose registers) are also saved by the Interrupt Service Routine itself.
   This saving process typically involves pushing these values onto the stack.
7. Vectoring to the ISR: The CPU determines the source of the interrupt (if multiple sources exist) and finds the starting memory address of the corresponding Interrupt Service Routine (ISR). This is often done via an Interrupt Vector Table, which is a predefined table in memory containing the starting addresses (vectors) of all ISRs. Each interrupt source has a unique entry (vector) in this table.
8. Numerical Example (Interrupt Vector Table): Assume an 8-bit microcontroller where Interrupt 0 (external interrupt) has a vector address of 0003H and Timer 0 interrupt has a vector address of 000BH. If Interrupt 0 occurs, the CPU will fetch the 2-byte (or 3-byte, depending on architecture) address stored at 0003H and 0004H and load it into the Program Counter, effectively jumping to the ISR for Interrupt 0.
9. ISR Execution: The CPU jumps to and begins executing the instructions within the Interrupt Service Routine. The ISR performs the necessary actions to service the interrupt (e.g., read data from a port, clear a timer flag, update a counter).
10. Context Restoration (POPping Registers): Before returning, the ISR restores the saved context by popping the register values back from the stack into their original registers.
11. Return from Interrupt: The ISR ends with a special "Return From Interrupt" (e.g., RETI or IRET) instruction. This instruction not only restores the Program Counter and Flag Register (which were typically saved automatically) but also re-enables interrupts (if they were disabled automatically upon entering the ISR) and allows the CPU to resume normal program execution precisely from where it was interrupted.

An Interrupt Service Routine (ISR), also known as an Interrupt Handler, is a dedicated block of code specifically written to respond to a particular interrupt event.

• Key Characteristics:
• Event-Driven: It only executes when its corresponding interrupt occurs.
• Atomic Operations: ISRs should be as short and efficient as possible to minimize the disruption to the main program flow. Long ISRs can negatively impact real-time performance.
• Context Preservation: The first few instructions of an ISR typically save any CPU registers that the ISR will use, and the last few instructions restore them, ensuring that the main program's context is not corrupted.
• Clearing Flags: The ISR must clear the interrupt flag that caused the interrupt; otherwise, the same interrupt will be triggered repeatedly immediately after returning.