The 8087 was meticulously engineered for tight coupling with the 8086/8088, often sharing the same physical address and data buses to facilitate seamless communication and cooperation.

Shared Bus Interface (Passive Monitoring)

Both the 8086/8088 CPU and the 8087 coprocessor are connected in parallel to the system's address and data buses. This allows the 8087 to continuously "listen" or "snoop" on the bus activity of the main CPU.

Instruction Queue Snooping and Co-detection

The 8086/8088 incorporates an internal instruction queue (a pre-fetch buffer). The 8087 also monitors this queue in real-time. When the 8086/8088 fetches an instruction from memory and places it into its queue, both the 8086/8088 and the 8087 simultaneously inspect the opcode of that instruction.

The ESC (Escape) Instruction - The Delegation Signal

The brilliance of the 8087's integration lies in the ESC (Escape) instruction. The 8086/8088 microprocessor is hardwired to recognize this special opcode. When the 8086/8088 encounters an ESC instruction in its instruction stream, it immediately understands that the subsequent bytes following the ESC are not standard 8086/8088 instructions. Instead, these bytes constitute the actual opcode and operand information for a floating-point instruction intended solely for the 8087.

Upon detecting ESC, the 8086/8088 essentially "steps aside" for the arithmetic part. It either ignores the subsequent bytes (if they are only FPU-specific opcodes) or, critically, it performs any necessary memory read or write cycles that might be indicated by the FPU instruction (e.g., an FPU instruction might require fetching a floating-point number from RAM). The 8086/8088 generates the address and control signals for these memory operations, but it does not interpret or execute the FPU-specific operation itself.

Concurrent with this, the 8087, also having seen the ESC and the subsequent FPU-specific instruction bytes, takes over execution of that particular floating-point command. It fetches its own operands from memory (often using the main CPU's bus signals for addressing) and performs the calculation.

TEST Pin and BUSY Signal (Synchronization Mechanism)

The 8087 possesses a dedicated BUSY output pin. This pin is asserted (pulled to a logic LOW) by the 8087 whenever it is actively engaged in executing a floating-point instruction and thus cannot accept a new command. The 8086/8088 microprocessor has a corresponding TEST input pin. The 8086/8088 provides a special instruction called WAIT. When the 8086/8088 executes a WAIT instruction, it suspends its own execution and enters an idle state. It will remain in this halted state until its TEST pin goes to a logic HIGH level.

The Linkage

In a typical 8087/8086 system, the 8087's BUSY output pin is directly connected to the 8086/8088's TEST input pin. This vital connection forms the primary hardware-level synchronization mechanism. A common programming pattern is for the 8086/8088 to issue an FPU instruction (via ESC), then immediately execute a WAIT instruction. This causes the CPU to pause until the 8087 finishes its potentially long computation and deasserts its BUSY signal, ensuring that the main CPU does not attempt to use the FPU's result before it is ready or issue another FPU command too soon.

RQ/GT (Request/Grant) Lines (Bus Arbitration for Coprocessor Memory Access)

While the 8087 is primarily a coprocessor to the 8086/8088, it often needs to access memory independently to fetch its own floating-point operands or to store its calculated results. Since it shares the main system buses with the 8086/8088, a mini-arbitration mechanism is required. The 8087 uses its RQ/GT (Request/Grant) lines to initiate bus requests to the 8086/8088. If the 8086/8088 is not currently using the bus, it can grant bus control to the 8087, allowing the coprocessor to perform its direct memory access (DMA-like) operations without the main CPU's explicit intervention for each memory cycle. Once the 8087 completes its memory access, it relinquishes the bus.

A major advantage of the 8087 (and any FPU) is its ability to directly handle a rich array of numerical data types, especially the complex floating-point formats, adhering strictly to the IEEE 754 standard for binary floating-point arithmetic. This standard ensures numerical precision, range, and consistent behavior across different hardware platforms.

Integer Types (for Loading/Storing to FPU Registers)

The 8087 can load and store integer values from memory and automatically convert them to its internal extended-precision floating-point format for calculation, or convert results back to integers for storage.
- Word Integer: 16 bits. Can represent signed integers from -32,768 to +32,767.
- Short Integer (Double Word Integer): 32 bits. Can represent signed integers from approximately ±2,000,000,000.
- Long Integer (Quad Word Integer): 64 bits. Can represent signed integers from approximately ±9,000,000,000,000,000,000.

Packed BCD (Binary Coded Decimal):

• Representation: 10 bytes (80 bits) where two decimal digits are packed into each byte (0-99). The most significant bit of the 10th byte indicates the sign.
• Range: Can represent up to 18 decimal digits precisely.

Floating-Point Types (The Core Strength, IEEE 754 Standard):

These are the primary data types for which the 8087 provides hardware acceleration.
- Single Precision (32-bit Floating-Point):
- Format: Represented by 32 bits with specific bits allotted for sign, exponent, and mantissa.
- Range: Approximately ±1.18 × 10−38 to ±3.40 × 10^38.
- Double Precision (64-bit Floating-Point):
- Format: Represented by 64 bits, offering greater precision.
- Range: Approximately ±2.23 × 10−308 to ±1.80 × 10^308.
- Extended Precision (80-bit Floating-Point):
- Format: 80 bits, used internally for calculations to minimize rounding errors and ensure higher accuracy when converted back.

The 8087 features a rich and powerful instruction set specifically designed for numerical computations. Its internal architecture includes an 8-level, deep floating-point stack. Most instructions implicitly operate on the top of this stack (ST(0)), and often on the next element (ST(1)). All 8087 instructions begin with the letter 'F'.

Data Transfer Instructions:

• FLD src: Floating-point Load. Pushes the src operand onto the top of the 8087's stack.
• FST dst: Stores the value from ST(0) into dst in memory.
• FSTP dst: Stores the value and pops the stack.
• FILD src: Loads integers from memory and converts them to floating-point.
• FIST dst: Converts ST(0) to integer and stores it in dst.

Basic Arithmetic Instructions:

• FADD src: Adds src to ST(0).
• FSUB src: Subtracts src from ST(0).
• FMUL src: Multiplies ST(0) by src.
• FDIV src: Divides ST(0) by src.
• FSQRT: Replaces ST(0) with its square root.

Transcendental Instructions:

• FSIN: Computes the sine of ST(0).
• FCOS: Computes the cosine of ST(0).
• FPTAN: Computes the tangent of ST(0).

Comparison and Control Instructions:

• FCOM src: Compares ST(0) with src.
• FNOP: No operation.
• FINIT: Resets the 8087 to its default state.

The effective utilization of an arithmetic coprocessor like the 8087 hinges on a tightly coordinated, synergistic approach where the main CPU and the coprocessor seamlessly share workload.

Assembly Language Integration:

For programmers writing in assembly language, the integration is direct. The assembler recognizes both 8086/8088 instructions and 8087 instructions. When it encounters an 8087 mnemonic, it translates the 8087 instruction into the special ESC opcode followed by the specific bit pattern for the instruction.

High-Level Language (HLL) Support:

Modern compilers automatically translate floating-point operations into corresponding FPU instructions when configured for a system with a coprocessor.

Synchronization (The WAIT Instruction's Critical Role):

The WAIT instruction is central for ensuring that the CPU does not use results from the coprocessor until the computation is finished. This avoids errors that can occur if the CPU tries to read invalid data before it’s ready.