This is the most fundamental shift in recent decades. Instead of solely increasing single-core clock speeds, processors now integrate multiple independent CPU cores onto a single chip. Each core can execute instructions independently, enabling true parallel execution of multiple tasks or threads. This addresses the 'power wall' (difficulty in increasing clock speeds further without excessive heat) by relying on parallelism rather than serial speed.

The cache hierarchy has become deeper (L1, L2, L3, sometimes L4) and cache sizes have grown significantly (up to hundreds of MBs of shared L3 cache) to further reduce memory access latency and handle larger working sets.

Processors continue to deepen their pipelines and add more parallel execution units (multiple integer ALUs, multiple FPUs, dedicated load/store units, branch units). This increases Instruction Level Parallelism (ILP), allowing more µops to be processed concurrently.

Modern processors use sophisticated OOO engines. They don't simply execute instructions in the program's sequential order. Instead, they analyze the µops, identify dependencies, and execute independent µops whenever their required resources are available, even if they appear later in the program code. The results are then reordered to appear as if they executed in program order. This maximizes utilization of execution units.

This has become extremely advanced. Processors aggressively predict branches, memory accesses, and even data values, then speculatively execute instructions based on these predictions. If a prediction is wrong, the speculative work is rolled back. This pushes the boundaries of performance but has also introduced security challenges (e.g., Spectre, Meltdown vulnerabilities) that require architectural mitigations.

Building on the MMX concept, modern CPUs include much more powerful SIMD instruction sets like Streaming SIMD Extensions (SSE, various versions), Advanced Vector Extensions (AVX, AVX2, AVX-512), and ARM's NEON. These extensions feature wider registers (128-bit, 256-bit, 512-bit) that can pack even more data elements (e.g., 16 x 32-bit integers or 32 x 16-bit integers) and perform parallel operations on them, providing massive speedups for highly parallelizable tasks in multimedia, scientific computing, deep learning, and cryptography.

Beyond general-purpose CPU cores, modern System-on-Chips (SoCs) and even CPU packages integrate dedicated hardware accelerators for specific, computationally intensive tasks: Graphics Processing Units (GPUs), Neural Processing Units (NPUs), and Digital Signal Processors (DSPs).

With the rise of mobile devices and large data centers, power consumption has become a critical design constraint. Modern architectures employ numerous techniques to improve energy efficiency: Clock Gating, Power Gating, Dynamic Voltage and Frequency Scaling (DVFS), and Dark Silicon.

Growing awareness of security threats has led to architectural enhancements like Intel Software Guard Extensions (SGX) and AMD Secure Encrypted Virtualization (SEV), which aim to create secure enclaves or protect virtual machines from attacks, even from compromised operating systems.