7.4.4. Completeness of Verification

Try these first

1. 1.

   What is meant by completeness of verification?

   Hint

   Think about what it means to check everything.

2. 2.

   Define a counterexample.

   Hint

   It involves demonstrating a failure or incorrect situation.

3. 3.

   What does completeness of verification assure?

   • Compliance with specifications
   • Limited testing scenarios
   • Increased simulation time

   Hint

   Consider what completeness guarantees in the context of verification.

4. 4.

   True or False: A counterexample is a positive outcome in formal verification.

   • True
   • False

   Hint

   Counterexamples usually indicate problems rather than confirmations.

5. 5.

   Consider a digital circuit designed to prevent overflow in a register. What formal methods might you use to ensure completeness, and what counterexamples could demonstrate possible failures?

   Hint

   Think about what inputs could potentially challenge the design's bounds.

6. 6.

   Design a verification strategy for a traffic light controller to ensure all states (green, yellow, red) are correctly handled without any unplanned transitions.

   Hint

   What specific conditions must be verified to prevent unsafe situations?