7.3.2. Property Checking

Property checking is the process of verifying that a given set of properties (or assertions) hold true throughout the design. These properties are often specified using temporal logic, such as Linear Temporal Logic (LTL) or Computation Tree Logic (CTL).

Property checking involves ensuring that certain conditions or properties are always met throughout the operation of a design. Designers define these properties using specialized languages, like Linear Temporal Logic (LTL) or Computation Tree Logic (CTL), which allow them to express how the design should behave over time.

Think of property checking like setting rules for a game. For example, you might declare, 'The ball must not cross the goal line unless the game is in progress.' Similarly, in design practices, we want to ensure certain conditions are true at all times, just like you want to keep the ball in the game.

● Property Types: ○ Safety Properties: Ensure that something bad never happens (e.g., a signal should never go high unless certain conditions are met). ○ Liveness Properties: Ensure that something good eventually happens (e.g., a process should eventually complete).

There are two main types of properties in property checking. Safety properties protect against undesirable states, such as ensuring that an error signal doesn't activate unless specific conditions are met. Liveness properties, on the other hand, guarantee that certain favorable outcomes happen eventually, like ensuring that a processing task will finish, thus leading to successful completion.

Imagine you're cooking a dish. A safety property would mean not allowing the stove to reach too high of a temperature (ensuring the dish doesn't burn), while a liveness property would mean ensuring that the dish eventually gets cooked and served (ensuring the meal is prepared).

● Process: ○ Assertions: Assertions are written in the design code to define desired behavior. Formal verification tools then check whether these assertions hold true in all possible states of the design.

To check properties, engineers write assertions directly into their design code. These assertions express the expected behavior of the design, acting as rules to verify against. After this, formal verification tools use mathematical techniques to explore every possible state of the design and confirm that all the assertions hold true. If even one assertion fails, it indicates a design error that needs to be addressed.

Consider a security alarm in a house. An assertion might be 'The alarm should sound if any door is opened while the security system is activated.' Just like how the alarm checks this condition, property checking tools verify that all specified rules in a design are continuously adhered to.

● Tools: Cadence JasperGold, Mentor Graphics Questa Formal, Synopsys Formality, and Xilinx Vivado are widely used for property checking.

There are several formal verification tools available that specialize in property checking. These tools, like Cadence JasperGold and Mentor Graphics Questa Formal, provide a variety of functionalities to help design engineers define, check, and validate their properties. They streamline the verification process, allowing for efficient checking against the defined assertions.

Using a GPS navigation system when driving is akin to using verification tools. Just as a GPS checks your route against live traffic conditions to ensure you're making the right turns, property checking tools evaluate designs against predefined rules to ensure they operate correctly in all scenarios.

Example of Property Checking in Verilog: // Safety property: signal_a should never be high when reset is low assert property (@(posedge clk) reset == 0 |-> signal_a == 0);

This Verilog snippet is an assertion that defines a safety property, saying that at every positive clock edge (indicated by @(posedge clk)), the signal 'signal_a' must be zero when 'reset' is low. This is a clear, executable statement that formal verification tools can check against every possible scenario in the design.

Imagine you have a safety switch for a light bulb that states, 'The light should not turn on if the safety switch is off.' This assertion ensures safety in the design just like the Verilog code helps avoid undesirable states in hardware design.

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