3.3.1. wire and reg

Try these first

1. 1.

   What type of data does a 'wire' in Verilog represent?

   Hint

   Remember, is it a conduit or a storage?

2. 2.

   What is the purpose of 'reg' in Verilog?

   Hint

   Think about what you want to remember in a circuit.

3. 3.

   What does 'wire' in Verilog do?

   • Stores data
   • Connects components
   • Both

   Hint

   Is it a storage type or a connector?

4. 4.

   Is 'reg' capable of storing values?

   • True
   • False

   Hint

   Think about a type that retains its state.

5. 5.

   Design a small Verilog module that includes a wire and a reg. Illustrate how signals flow through the wire while showing how the reg retains state.

   Hint

   Consider how you would use both types in a single circuit function.

6. 6.

   Write a function where changing the value of a reg affects a wire. Demonstrate how the values transition during clock cycles in a simulation.

   Hint

   Link how changes propagate through the system.