3.2. Verilog Language Basics

Verilog code is structured into modules, which are the basic building blocks of a design. Each module can have inputs and outputs, and can instantiate other modules to build complex designs.

In Verilog, a module acts like a fundamental unit that encapsulates functionality. Think of it as a small building block in a larger structure. Each module can have its own inputs (signals coming in) and outputs (signals going out), and can include other modules to form complex systems. This modular approach allows for better organization and reusability of code.

Imagine building a house. Each room in the house (like a kitchen, bedroom, or bathroom) is similar to a module in Verilog, having its own purpose (inputs and outputs). By combining these rooms, you can create a complete living space, just as modules combine to form a complete digital design.

A Verilog module is the fundamental unit in Verilog. It encapsulates a piece of functionality, such as a flip-flop or an ALU, and defines the interface through ports.

module module_name (
input wire [3:0] input_a, // 4-bit input
input wire input_b, // 1-bit input
output wire [7:0] output_c // 8-bit output
);
// Internal logic goes here
endmodule

• module_name is the name of the module.
• input and output are ports for the module.
• wire and reg are the types of variables used in Verilog.

When defining a module in Verilog, you start with the keyword 'module' followed by the module's name, which is how you will refer to it later. Inputs and outputs are specified within parentheses and include their types and bit sizes. Internal logic, which describes how the inputs are transformed into outputs, can be described in the body of the module that lies between 'begin' and 'end'. This structure allows engineers to encapsulate specific functionalities, such as how data is processed through a flip-flop or arithmetic logic unit (ALU).

Think of the module as a recipe for making a cake. The module's name is like the recipe name. The ingredients (inputs) are what you need to start baking, while the cake itself (output) is what you end up with. The steps you follow (internal logic) are like the instructions in the recipe that guide you on how to combine everything to create the final product.

• Inputs: Represent signals coming into the module.
• Outputs: Represent signals leaving the module.
• Inouts: Bi-directional signals, often used in buses.
• Register (reg): Used to store values that can be updated in procedural blocks (e.g., always block).
• Wire (wire): Used for continuous assignments and cannot store values.

Ports are crucial in module definitions. Inputs are signals that bring information into the module, while outputs send processed information out. Inouts allow signals to both enter and exit the module, useful for situations where communication goes in both directions. The 'reg' type is used when you need to store values that may change whenever a specific event occurs in the design, whereas 'wire' types are for connections that pass values continuously but do not store them.

Imagine a factory assembly line. The inputs represent raw materials delivered to the conveyor belt, while outputs are the finished products that come out at the end. Inouts are like workers that can both take items from the conveyor belt and put items back. 'Wire' is like a pipe that transports water continuously, while 'reg' is like a container that holds water until it's needed elsewhere.

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