3.2. Verilog Language Basics

Try these first

1. 1.

   What is a module in Verilog?

   Hint

   Think of a module as an independent unit in your design.

2. 2.

   Name one type of port in Verilog.

   Hint

   Consider how data enters and exits modules.

3. 3.

   What does a module represent in Verilog?

   • Data type
   • Building block
   • Signal

   Hint

   Consider the concept of structure in your design.

4. 4.

   True or False: An 'inout' port can only send signals out of a module.

   • True
   • False

   Hint

   Think about how it communicates.

5. 5.

   Design a Verilog module that combines multiple input types into one output signal. Include at least three inputs and describe how they interact.

   Hint

   Think about how inputs can logically combine to determine an output.

6. 6.

   Create a test module that validates the functionality of the previous combiner module. What signals would you need to apply, and how would you verify the outputs?

   Hint

   Consider applying both edge cases and typical use cases for thorough validation.