3.6. Finite State Machine (FSM) Design in Verilog

FSMs are commonly used in digital design to model sequential logic, like control units in processors or protocol controllers. Verilog can be used to design both Mealy and Moore type FSMs.

A Finite State Machine (FSM) is a model used in digital design that represents states and transitions between those states. It's particularly useful for controlling devices or systems that respond to differing inputs, like how a remote control communicates with a television. FSMs can be categorized as Mealy or Moore machines depending on how they respond to inputs: Mealy machines respond to inputs immediately, while Moore machines respond with outputs based only on the current state.

Imagine a traffic light system as an FSM. The light can be in one of three states: red, yellow, or green. The transitions from one light to the next depend on a timer or a button press, which can be seen as inputs triggering those transitions. This makes it easier to design complex control systems in a logical way.

module fsm ( input wire clk, input wire reset, input wire start, output reg [1:0] state ); // State Encoding parameter IDLE = 2'b00, RUN = 2'b01, DONE = 2'b10; always @(posedge clk or posedge reset) begin if (reset) state <= IDLE; else begin case (state) IDLE: if (start) state <= RUN; RUN: state <= DONE; DONE: state <= IDLE; default: state <= IDLE; endcase end end endmodule

In this Verilog module for a Moore machine, the FSM is defined with inputs for clock (clk), reset, and a start signal, and it outputs the current state as a 2-bit register. The states are encoded as parameters for better readability. The always block describes how the state changes: on a clock edge or when reset is high, it checks the current state. Depending on what state the FSM is currently in, and if the start signal is activated, it defines how to transition to the next appropriate state. The default case prevents undefined behavior.

Consider a game scoreboard as a Moore FSM. The scoreboard is continually updated every time a goal is scored (triggered by the clock), and the score will reset if the game is restarted (using the reset input). Depending on the current score state (IDLE, RUN, DONE), it shows different messages, such as 'Game Over' or 'Next Round'. Each score update is a transition from one state to another based on actions that occur in the game.

● FSM states are defined as parameters, and state transitions are controlled based on the current state and input signals. ● Edge-sensitive operations are used in the always block to trigger state changes based on the clock signal.

In FSM design, defining states with parameters improves code readability and maintainability. In the provided example, states like IDLE, RUN, and DONE are declared as parameters. This enables easy updates or changes to state encodings. Transitions between these states are contingent upon both the state the FSM is currently in and the input signals (like start). By using edge-sensitive operations in the always block, we ensure that state changes occur precisely at defined moments, such as the rising edge of the clock signal.

Think of a light switch: it has different states, such as 'off' and 'on.' The switch's position affects the light's state. When the switch is pressed (an input signal), it transitions from ‘off’ to ‘on’ (state transition) based on the given rules (the mechanics of pressing the switch). Just like how the light's state changes with the switch action, the FSM toggles between states based on input signals at specific clock edges.

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