Practice Objective (4.2.1) - Design and Simulation of Basic Combinational CMOS Logic Gates (NAND/NOR)
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Objective

Practice - Objective - 4.2.1

Learning

Practice Questions

Test your understanding with targeted questions

Question 1 Easy

What is the output of a NAND gate with inputs A=1, B=0?

💡 Hint: Remember that NAND outputs low only for inputs both being high.

Question 2 Easy

Define a NOR gate.

💡 Hint: Think about the conditions for a high output.

4 more questions available

Interactive Quizzes

Quick quizzes to reinforce your learning

Question 1

What type of logic gate outputs low only when all inputs are high?

AND
NAND
NOR

💡 Hint: Consider the truth table of each gate.

Question 2

True or False: A NOR gate will always output a low signal if at least one input is high.

True
False

💡 Hint: Examine the conditions for a high output in the truth table.

2 more questions available

Challenge Problems

Push your limits with advanced challenges

Challenge 1 Hard

Given a complex logic circuit with NAND and NOR gates, derive the output for all combinations of inputs and identify its main gate type.

💡 Hint: Systematically evaluate one input combination at a time.

Challenge 2 Hard

Refactor a NAND gate circuit to optimize its size while maintaining speed, and justify each sizing decision.

💡 Hint: Focus on balancing NMOS and PMOS widths for best performance.

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Reference links

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