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Interactive Audio Lesson
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Schematic Capture and Pre-Layout Simulation
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Today, we will begin with the schematic capture of a 2-input NAND gate. Can anyone explain what we mean by schematic capture?
I think it's about creating a visual representation of the circuit using symbols for each component.
Correct! A schematic shows how the components connect. We must include two NMOS transistors in series and two PMOS in parallel for our NAND gate. What is the significance of their arrangements?
The output only goes low when both inputs are high, right?
Exactly! After the schematic, we run pre-layout simulations. Why is this step important?
To ensure the design meets our expected performance before we move to layout, right?
Absolutely. Let's remember: simulate before layout to avoid costly errors! Now, who can tell me how we measure delay in our simulations?
We look at the time it takes for the input changes to reflect in the output, like tpLH and tpHL.
Great job! Delay measurements are crucial for understanding circuit speed. In summary, we need to properly capture the schematic and perform pre-layout simulations to ensure correctness.
Full-Custom Layout Design of NAND Gate
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Now that we've checked our schematic, we move on to layout design. What does a full-custom layout entail?
It means we design everything from scratch, considering every detail like the placement of transistors and the connections between them.
Exactly! We need to strategically place power and ground connections. Can anyone tell me why shared diffusion is beneficial?
It reduces area and parasitic capacitance, which helps speed up the circuit.
Well done! Minimizing parasitics is key. As we arrange our layout, what placements are vital for making clean connections?
Well/substrate contacts and diffusion_contacts are crucial to ensure everything connects properly.
Right! We need to be diligent here. To sum up, creating a full-custom layout involves strategic placement to enhance performance and minimize parasitics.
Physical Verification - DRC and LVS
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Once our layout is complete, we need to verify it against design rules. Who remembers what DRC stands for?
Design Rule Check!
Correct! DRC checks for geometric issues in the layout. What kinds of errors might it catch?
Well, it can find errors related to minimum widths, spacing, and overlaps.
Exactly! And then we have LVS, which stands for Layout Versus Schematic. Why is LVS important?
LVS checks that what we've laid out physically matches our schematic in terms of connectivity and specifications.
Exactly! Debugging LVS errors might be tough, but it’s crucial for a successful design. To recap, both DRC and LVS validate our designs before we proceed.
Post-Layout Simulation
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Finally, after DRC and LVS, we conduct a post-layout simulation. What is the reasoning behind performing this step?
To include parasitic effects that weren’t accounted for in the pre-layout simulation, making it more realistic.
Exactly! Parasitic extraction is essential. Can someone explain how this affects our delay measurements?
Post-layout delays are usually higher due to the added capacitance and resistance from the layout.
Perfect! It helps us understand the practical implications of our design. In summary, post-layout simulations give us a clearer picture of actual circuit performance.
Introduction & Overview
Read a summary of the section's main ideas. Choose from Basic, Medium, or Detailed.
Quick Overview
Standard
The section summarizes the experimental procedures involved in creating and verifying the layout of 2-input NAND and NOR gates, from schematic capture and pre-layout simulations to full-custom layout design, physical verification, and post-layout simulation. It includes crucial checkpoint activities such as Design Rule Checks (DRC) and Layout Versus Schematic (LVS) to ensure accuracy and adherence to design rules.
Detailed
Detailed Summary
This section provides a structured approach to the Procedure of designing and verifying CMOS logic gates, specifically focusing on 2-input NAND and NOR gates. It is divided into multiple tasks that guide students through the experimental steps:
Task 1: Schematic Capture of 2-input NAND Gate and Pre-Layout Simulation
Students launch their EDA environment, create a new cell view, draw the NAND gate schematic with properly connected transistors, and run pre-layout functional simulations to ensure correctness of functionality and measure delays.
Task 2: Full-Custom Layout Design of 2-input NAND Gate
In this task, students create the layout view for the NAND gate, considering factors such as power rail placement, transistor stacking, shared diffusion regions, and the addition of proper well contacts.
Task 3: Physical Verification - Design Rule Check (DRC)
Students run DRC to verify adherence to design rules, analyze errors, and modify layouts accordingly to achieve a DRC-clean status.
Task 4: Physical Verification - Layout Versus Schematic (LVS)
This task involves confirming that the layout matches the schematic in terms of connectivity and component parameters through LVS analysis.
Task 5: Post-Layout Simulation for NAND Gate
After ensuring DRC and LVS compliance, students perform parasitic extraction and run post-layout simulations that include parasitic components to verify performance metrics.
Task 6: Repeat for 2-input NOR Gate
Students replicate the process outlined in previous tasks for the NOR gate, emphasizing the difference in transistor arrangement and the importance of design rules and verification steps inherent to this gate design.
Overall, this section is critical in building hands-on experience with CMOS logic gate design and reinforces the principles of layout design, verification, and performance analysis.
Audio Book
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Task 1: Schematic Capture of 2-input NAND Gate and Pre-Layout Simulation
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- Launch EDA Environment and Create New Cell View:
- Log in and navigate to your lab directory: cd ~/vlsi_lab/lab7_combinational_gates
- Launch your main EDA tool.
- Create a new schematic cell view for your 2-input NAND gate:
- Library: mylib
- Cell Name: nand2
- View: schematic
- Draw the 2-input NAND Gate Schematic:
- Place two NMOS transistors (MN1, MN2) and two PMOS transistors (MP1, MP2).
- Connect the NMOS transistors in series for the pull-down network. Connect the PMOS transistors in parallel for the pull-up network.
- Connect their gates to form inputs A and B.
- Connect the output Y.
- Add VDD and GND power pins.
- Transistor Sizing: For initial design, use default or minimum L (e.g., 0.18u). For W, consider sizing for roughly balanced drive strength. For NAND2: NMOS typically W = 0.5u (for each in series), PMOS typically W = 1.0u (for each in parallel). (Adjust based on your PDK's nominal sizes).
- Perform Pre-Layout Functional and Delay Simulation:
- Create a new schematic cell view for a test bench (e.g., nand2_tb).
- Instantiate your nand2 schematic.
- Add pulse voltage sources for inputs A and B to generate all 4 input combinations (00, 01, 10, 11).
- Add VDD and GND sources.
- Add a load capacitance (e.g., 10fF or 20fF) at the output Y to simulate typical gate loading.
- Configure a Transient Analysis to simulate for a few nanoseconds.
- Run Simulation.
- Verify Functionality: Check the output waveform Y against the truth table of a NAND gate.
- Measure Delay: Using the waveform viewer, measure the propagation delay (tpLH and tpHL) from input transitions (A or B) to the output Y for critical paths. Document these pre-layout delay values.
- Capture screenshots of your schematic and simulated waveforms.
Detailed Explanation
In this chunk, you initiate the design of a 2-input NAND gate by first creating a structured environment for your schematic. You log into the Electronic Design Automation (EDA) tool and create a new cell for your NAND gate design. Following that, you draw the gate's schematic by placing two NMOS and two PMOS transistors in the required configuration: NMOS in series (for a pull-down network) and PMOS in parallel (for a pull-up network). You then set up a test bench to simulate the gate's function, applying various input combinations and measuring output delays. The goal is to confirm that your design functions appropriately before moving onto the physical layout stage.
Examples & Analogies
Think of designing the 2-input NAND gate like building a complex LEGO structure. First, you gather all the LEGO pieces (your components), and then you follow a manual (the schematic) that tells you exactly how to connect the pieces together to achieve the final model. Just as you would carefully align each piece to ensure a solid build, you meticulously draw your schematic to make sure all transistors connect correctly, ensuring the gate operates as intended.
Task 2: Full-Custom Layout Design of 2-input NAND Gate
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- Create New Layout Cell View:
- Create a new layout cell view for your NAND gate:
- Library: mylib
- Cell Name: nand2
- View: layout (ensure it's the layout view for the same cell name as your schematic for LVS).
- Draw the Layout - Strategic Placement:
- Power Rails: Begin by drawing VDD and GND metal1 rails at the top and bottom of your layout area.
- N-Well: Draw the nwell region large enough to contain your two PMOS transistors and their n_diffusion well contacts.
- NMOS Placement (Series): Draw two n_diffusion rectangles for MN1 and MN2. These can be placed such that their drains are shared (abutted) to save area and contacts. Draw two separate vertical poly stripes crossing these diffusions for inputs A and B. The source of one NMOS connects to GND, the source/drain interface connects to the other NMOS, and the drain of the second NMOS connects to the output Y.
- PMOS Placement (Parallel): Draw two p_diffusion rectangles for MP1 and MP2 inside the nwell. These should be separated. Draw two separate vertical poly stripes crossing these diffusions for inputs A and B. Both PMOS sources connect to VDD, and both PMOS drains connect to the output Y.
- Common Centroid/Symmetry (Optional, but Recommended for Learning): Consider if you can arrange your A and B inputs symmetrically for better matching (e.g., A-B-B-A poly ordering, or interleaving if applicable). For a simple NAND2, direct shared diffusion is usually the primary optimization.
- Add Contacts: Place diffusion_contacts to connect source/drain diffusions to Metal1, and poly_contacts to connect polysilicon gates to Metal1.
- Add Well/Substrate Contacts: Crucially, add n_diffusion (with contacts) connected to VDD within the N-well, and p_diffusion (with contacts) connected to GND in the P-substrate region. Place these sufficiently close to the active devices.
- Routing (Metal1): Draw metal1 lines to connect all components according to the NAND2 schematic:
- Connect gates to their respective input pins (A, B).
- Connect NMOS source to GND rail.
- Connect PMOS source to VDD rail.
- Connect the series NMOS drain-to-source interface.
- Connect the parallel PMOS drains and the series NMOS drain to the common output Y trace.
- Layout Pins: Create layout pins (on metal1) for A, B, Y, VDD, GND.
- Save Your Layout: Frequently save your design.
Detailed Explanation
This portion focuses on the physical layout of the 2-input NAND gate. After creating the layout cell view, you begin by systematically drawing the physical placement of components. This includes defining spaces for power rails, placing transistors appropriately to optimize area and connections, and ensuring everything is connected as per the schematic design you made earlier. It's essential to consider strategies like shared diffusion to minimize area and potential parasitics. The proper arrangement of all these elements is crucial for functionality and manufacturability.
Examples & Analogies
Imagine you are organizing an intricate puzzle on a table. You need to arrange the puzzle pieces (transistors) correctly by understanding how each piece fits together while keeping enough space for the borders (power rails). If you were building this puzzle in a small area, you would want to share border pieces (shared diffusion) to make efficient use of space, avoiding unnecessary gaps that could complicate the overall picture (circuit performance). This careful consideration in layout design is similar to how you would arrange your puzzle pieces for the best fit.
Task 3: Physical Verification - Design Rule Check (DRC)
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- Run DRC: Initiate the DRC tool from your layout editor.
- Analyze and Correct DRC Errors:
- Systematically go through all reported DRC errors (e.g., minimum width, spacing, enclosure, overlap, density, well spacing).
- Locate each error on the layout (using the error browser or markers).
- Understand the specific rule violation by referring to your design rules.
- Carefully modify your layout to resolve each error. This will involve stretching, moving, or resizing shapes.
- Iterate: Save your layout and re-run DRC after each set of corrections. Continue until your nand2 layout is completely DRC-clean. Document the types of errors you encountered and your correction strategies.
Detailed Explanation
In this chunk, the focus is on ensuring that the layout adheres to established design rules, which cover aspects such as minimum dimensions, spacing, and proper routing. By running the Design Rule Check (DRC), designers can identify violations that may prevent successful fabrication. Analyzing and correcting each reported error requires understanding the implications of each rule, making necessary adjustments, and refining the layout iteratively. The DRC process emphasizes the importance of verifying design integrity before manufacturing.
Examples & Analogies
Consider planning a construction project, like building a house. Before you can lay the foundation, you need to make sure the plans comply with building codes (like DRC). If blueprints have errors—say, the rooms are too close together or there isn’t enough space for wiring—you would need to redesign to meet those codes. Once all corrections are made and the designs are up to code, you can confidently build without fear of future complications. Just like in construction, the DRC process ensures the layout is ready for the next stages.
Task 4: Physical Verification - Layout Versus Schematic (LVS)
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- Launch LVS Tool:
- From your EDA environment, launch the LVS tool (e.g., Tools > LVS > Run LVS).
- Configure LVS:
- Specify the schematic view (nand2 in mylib) as the "Source" or "Schematic" input.
- Specify the layout view (nand2 in mylib) as the "Layout" input.
- Ensure the correct extraction and rule decks are loaded (usually handled by the PDK setup).
- Run LVS: Execute the LVS analysis.
- Analyze LVS Report:
- The LVS tool will generate a report indicating whether there is a "match" or "no match."
- If "Match": Congratulations! Your layout's connectivity matches your schematic. Proceed to post-layout simulation.
- If "No Match": This indicates a connectivity discrepancy. The report will detail the specific differences, such as:
- "Different number of instances" (e.g., missing transistor).
- "Mismatch in device parameters" (e.g., W/L of a transistor in layout doesn’t match schematic).
- "Missing connections" (an open circuit).
- "Extra connections" (a short circuit).
- "Mismatch in nets" (incorrect wiring).
- Debugging LVS Errors: This is often the most challenging part of layout verification.
- Use the LVS error browser to pinpoint the exact location of discrepancies on both your schematic and layout.
- Carefully compare the connections and parameters in your schematic to what is physically drawn in the layout.
- Common LVS errors include: forgetting contacts, miswiring, incorrect transistor W/L values, floating well/substrate contacts, and typos in pin names.
- Correct errors in your layout or schematic as needed. Save, and re-run LVS until a "match" is achieved. Document all LVS errors encountered and their resolutions.
Detailed Explanation
The focus here is on verifying that the physical layout corresponds accurately to the designed schematic using the Layout Versus Schematic (LVS) tool. The process involves configuring inputs for both the schematic and layout, running the analysis, and interpreting the results. A 'match' indicates that your design can proceed while a 'no match' requires debugging of any discrepancies noted in the report. Understanding and resolving these discrepancies is crucial for ensuring that the intended functionality of your schematic is preserved in the physical design.
Examples & Analogies
Think of LVS like checking a recipe before baking a cake. After shopping for ingredients (your schematic) and setting up your kitchen (your layout), you need to ensure you have everything you need according to your list. If you find that a crucial ingredient is missing or you have used the wrong amount, it’s crucial to correct it before baking (similar to getting a match in LVS). Just like baking a cake requires every component to work together seamlessly, your schematic and layout must match to function correctly.
Task 5: Post-Layout Simulation for NAND Gate
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- Perform Parasitic Extraction:
- From your DRC/LVS clean layout (nand2), initiate the parasitic extraction tool (e.g., PEX in Cadence, StarRC in Synopsys).
- This tool will analyze your layout and create a new extracted view (often called ext or calibre_view) which contains your original transistors PLUS all the calculated parasitic capacitances and resistances from your metal wires, contacts, and diffusion junctions.
- Create Post-Layout Test Bench:
- Create a new schematic test bench (e.g., nand2_post_layout_tb).
- Instantiate the Extracted View: Instead of instantiating your nand2 schematic, instantiate the newly created nand2 extracted view from your library. This ensures your simulation uses the most accurate parasitic models.
- Connect the pulse inputs, VDD, GND, and output load capacitance just like your pre-layout test bench.
- Run Post-Layout Transient Simulation:
- Configure and run a Transient Analysis similar to your pre-layout simulation.
- Analyze and Compare Results:
- Functional Verification: Confirm the output Y still follows the NAND gate truth table.
- Delay Analysis: Measure the propagation delays (tpLH, tpHL) from inputs to output.
- Critical Comparison: Compare these post-layout delays to your previously measured pre-layout delays.
- Observation: You should observe that post-layout delays are generally higher than pre-layout delays due to the inclusion of extracted parasitic capacitances and resistances.
- Quantification: Calculate the percentage increase in delay due to parasitics.
- Capture screenshots of your post-layout waveforms and note the measured delays.
Detailed Explanation
This section emphasizes the final testing of the NAND gate after layout verification, focusing on post-layout simulation. Once the layout passes DRC and LVS checks, parasitic extraction is conducted to account for additional resistances and capacitances introduced during the physical design. You create a new test bench for simulation using this extracted model, which will reflect real-world conditions more accurately than the pre-layout simulation. After running the simulation, you analyze the functional correctness and how the inclusion of parasitics has affected delay characteristics.
Examples & Analogies
Imagine you're test-driving a new car after it has been assembled. Just like you need to check if the car performs as expected under real driving conditions, post-layout simulation allows you to verify the circuit operates correctly in its intended environment. If you notice that the car takes longer to accelerate than expected (like delays caused by parasitics in your circuit), you can quantify how much those factors affect performance, ensuring that when you finally hit the road (or go to production), the car runs smoothly.
Task 6: Repeat for 2-input NOR Gate
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- Schematic Capture and Pre-Layout Simulation:
- Repeat Task 1 for a 2-input NOR gate. Remember the different series/parallel transistor configuration for NOR. Adjust transistor W/L ratios (e.g., NMOS in parallel, PMOS in series. For NOR2: NMOS W = 1.0u (each in parallel), PMOS W = 0.5u (each in series)).
- Perform pre-layout functional and delay simulation, documenting results.
- Full-Custom Layout Design:
- Repeat Task 2 for your nor2 gate. Pay close attention to routing for series PMOS and parallel NMOS, and effective use of shared diffusions.
- Physical Verification (DRC and LVS):
- Repeat Task 3 (DRC) and Task 4 (LVS) for your nor2 layout. Debug and resolve all errors until both checks pass.
- Post-Layout Simulation:
- Repeat Task 5 for your nor2 gate. Perform parasitic extraction and then post-layout transient simulation.
- Analyze delays and compare them with pre-layout results for the NOR gate.
- Capture all necessary screenshots.
Detailed Explanation
This section outlines the process for designing and verifying a 2-input NOR gate, mirroring the previous tasks completed for the NAND gate. You will capture the schematic and perform pre-layout simulation, making special adjustments necessary for the unique configurations of the NOR gate—which differs from the NAND in how transistors are arranged. Similar to the NAND gate's tasks, you'll repeat the layout design, physical verification, and post-layout simulation stages for the NOR gate, ensuring a comprehensive understanding of both gates.
Examples & Analogies
Think of this task as learning a different sport that has its own set of rules but is played similarly to one you already know. If you learned basketball (NAND gate) first, now you're learning soccer (NOR gate). The basic idea of playing—scoring goals or making shots—is the same, but the configurations and strategies (transistor arrangements) differ. Just as you adapt your skills to trace out the new field and game plan, you adapt your design process to accommodate the different needs of the NOR gate.
Definitions & Key Concepts
Learn essential terms and foundational ideas that form the basis of the topic.
Key Concepts
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Schematic Capture: The initial step of representing a circuit using symbols.
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Pre-Layout Simulation: Analyzing schematic designs before layout to verify functionality.
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Full-Custom Layout: Designing the layout from scratch with consideration for every aspect.
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Design Rule Check (DRC): Ensuring layout adheres to geometric rules.
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Layout Versus Schematic (LVS): Confirming layout matches the original schematic.
Examples & Real-Life Applications
See how the concepts apply in real-world scenarios to understand their practical implications.
Examples
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Creating a NAND gate schematic that properly connects two NMOS and two PMOS transistors.
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Performing parasitic extraction to measure the actual performance impacts on delay.
Memory Aids
Use mnemonics, acronyms, or visual cues to help remember key information more easily.
🎵 Rhymes Time
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Before you lay it out, check it all about; DRC will show, if you're in the know.
📖 Fascinating Stories
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Imagine building a house (the circuit). First, you sketch the blueprint (schematic), then check with city codes (DRC) before actual construction (layout).
🧠 Other Memory Gems
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Remember 'DRC and LVS' - 'Double+Check and Verify layouts Schematic!'
🎯 Super Acronyms
P.S.D. - Parasitic, Simulation, Design - to remember post-layout simulation steps!
Flash Cards
Review key concepts with flashcards.
Glossary of Terms
Review the Definitions for terms.
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Term: DRC
Definition:
Design Rule Check, a verification step to ensure all geometric layout rules are followed.
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Term: LVS
Definition:
Layout Versus Schematic, a check verifying that the physical layout corresponds to the intended schematic.
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Term: Parasitic Extraction
Definition:
The process of identifying and quantifying unintended capacitance and resistance in the layout.
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Term: PSubstrate
Definition:
The physical layer upon which PMOS transistors are built; it connects to GND.
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Term: NWell
Definition:
The region where PMOS transistors are placed; it connects to VDD.