Designing an operational amplifier from the ground up involves a systematic approach to each of its constituent stages, ensuring that individual stage performance contributes to the overall desired op-amp specifications.

The input differential amplifier is the "front end" of the op-amp, setting crucial parameters like input impedance, noise performance, offset voltage, and common-mode rejection. Its design is fundamental to the op-amp's overall quality.

1. Define Target Specifications: Before beginning the design, clearly define the performance goals for the differential input stage. These typically include: ● Desired Differential Voltage Gain (Ad): How much the stage should amplify the difference. ● Target Common Mode Rejection Ratio (CMRR): How well it should reject common-mode noise. ● Required Input Common Mode Range (ICMR): The permissible voltage swing on the common inputs. ● Input Bias Current (Ib) / Input Offset Current (Ios) limits: How much current the inputs draw. ● Input Offset Voltage (Vio) limits: The voltage required to null the output. ● Power Supply Voltages (Vcc, Vee): The available power rails.

1. Select Input Transistor Type (BJT vs. FET): ● BJTs: Offer lower input offset voltage, lower input noise current, and typically higher transconductance for a given current. Their main drawback is higher input bias current (due to base current) and lower input impedance compared to FETs. ● FETs (JFETs or MOSFETs): Provide extremely high input impedance (negligible gate current) and lower input noise voltage. However, they may have higher input offset voltage and lower transconductance than BJTs for the same current. The choice depends heavily on the primary op-amp application (e.g., BJT for general purpose, FET for high-impedance sensors).

1. Determine Tail Current (I_tail): ● The total quiescent current flowing through the common emitter/source connection of the differential pair (often provided by a current source) is the "tail current" (I_tail). This current is critical as it sets the quiescent operating current for each transistor (Ic for BJT, Id for FET). ● Typically, for a balanced design, this current is split equally between the two input transistors: Ic1 = Ic2 = I_C = I_tail / 2. ● Impact of I_tail: ■ Higher I_tail leads to higher gm (transconductance), which generally means higher differential gain and faster response. ■ However, higher I_tail also means higher power consumption and potentially higher noise. ■ A typical range for I_tail in general-purpose op-amps might be from tens of microamperes to a few milliamperes.

1. Calculate Collector/Drain Resistors (RC): ● These resistors (RC for BJT, RD for FET) convert the differential current changes into differential voltage changes. Their value directly impacts the differential gain. ● Formula for Differential Gain (Ad) with Differential Output: Ad = gm * RC ● Formula for Differential Gain (Ad) with Single-Ended Output: Ad = gm * RC / 2 (Since the output is taken from one side, you only see half the total differential swing relative to common). ● Rearranging for RC (for single-ended output, common in op-amp intermediate stages): RC = (2 * Ad_target) / gm.

1. Design the Common-Mode Current Source (or Determine Effective RE): ● This is crucial for achieving high CMRR. Instead of a simple resistor, an active current source (e.g., a simple BJT current mirror, a Widlar current source, or a Wilson current source) is almost always used for the tail current in high-performance op-amps. ● Reason for Active Current Source: An ideal current source has infinite output impedance. The output impedance of the current source effectively acts as the RE (common emitter/source resistance) in the common-mode gain formula. A larger RE results in a smaller Acm and thus a higher CMRR.

To meet a target CMRR, you can determine the required minimum effective output resistance of the current source: RE_effective_min = CMRR_target / (2 * gm). ● Current Source Selection: Choose a current source topology that provides the desired I_tail and has an output impedance (often the output resistance 'ro' of the current source transistor) that meets or exceeds RE_effective_min. More complex current sources (like Wilson or cascode current mirrors) offer higher output impedance for better CMRR.

The intermediate gain stages are responsible for providing the bulk of the op-amp's remarkably high open-loop voltage gain. They typically follow the differential input stage, often taking a single-ended output from it.

1. Maximize Voltage Gain: ● The primary objective is to achieve extremely high voltage gain. Traditional passive resistors as loads limit gain and consume valuable chip area. ● Active Loads (Current Mirrors): This is the almost universal solution in integrated circuit op-amps. Instead of a resistor, a current mirror (e.g., a simple two-transistor current mirror or a cascode current mirror) acts as the collector/drain load.

1. DC Level Shifting (for proper biasing of the output stage): ● The output of the differential input stage, and thus the input to the intermediate gain stage, often has a DC voltage level that is significantly above ground or the negative supply rail. ● The output stage, particularly a Class AB push-pull configuration, typically requires its input DC voltage to be near ground or the center of the supply rails for symmetrical output swings.

1. Minimal Loading Effects: The intermediate gain stage should be designed such that it is not heavily loaded by the subsequent output stage. This typically means the output stage should have a relatively high input impedance compared to the output impedance of the intermediate gain stage. Emitter followers (output stage) naturally provide high input impedance.

1. Bandwidth and Stability Considerations: The intermediate gain stage is where the dominant pole for frequency compensation is typically introduced (covered in section 7.4). Its design must account for the effects of internal parasitic capacitances and how they interact with the overall compensation strategy to ensure stable operation.

7.3.3 Design of Output Stages (Class A, AB for Driving Load): The final stage of the op-amp, the output stage, acts as a buffer and power amplifier. Its primary responsibility is to deliver sufficient current to the load at a low output impedance, while maintaining the linearity of the amplified signal.

1. Linearity and Efficiency: Choosing the Class of Operation: Output stage choices present trade-offs between linearity and efficiency. Class A provides high linearity but is inefficient; Class B offers higher efficiency but suffers from crossover distortion. Class AB is a compromise that balances the two.

Designing Class AB involves ensuring a quiescent bias current flows through both transistors even in the absence of a signal, eliminating crossover distortion while maintaining efficiency.

These principles underscore the comprehensive approach required to design effective OP-AMPs, ensuring that each design decision plays a crucial role in the amplifier's performance and efficiency.