15.3.4. Fetch and Execute Cycle

We know that while going to execute an Instruction, that Instruction Cycle is having basically 2 phases: one is your Fetch, second one is Execute. In the Fetch Cycle, we Fetch the Instruction from the Memory and bring it to the processor. Once we get the Instruction, our job is to execute that particular Instruction inside the processor.

In the fetch and execute cycle of a computer's instruction processing, two key phases exist: fetching and execution. The fetching phase is where the processor retrieves the instruction from memory. This instruction is stored in a specific location in memory, identified by an address. After fetching, the processor executes the instruction, which involves performing the operation specified by the instruction, such as arithmetic or logic operations.

Think of this process as a chef preparing a meal. The chef needs to fetch a recipe (fetching phase) from a cookbook before executing the steps needed to make the dish (execution phase). Just like the chef retrieves the recipe to know what ingredients to use and how to combine them, the processor fetches the instruction to know what task to perform.

During the fetch phase, the program counter (PC) holds the address of the next instruction. This address is sent to the Memory Address Register (MAR) to retrieve the instruction stored at that address. After fetching the instruction, the PC increments to point to the next instruction. The instruction is then placed into the Instruction Register (IR) for execution.

In the fetch phase, the Program Counter (PC), which tracks where the CPU is in the instruction sequence, sends its current value to the Memory Address Register (MAR). The MAR accesses the memory to fetch the instruction at that address. Once the instruction is retrieved, the PC increments by one, preparing it for the next cycle. This fetched instruction is then stored in the Instruction Register (IR). In the execution phase, this instruction is decoded and executed by the CPU.

Consider the example of a librarian retrieving books. The librarian (similar to the CPU) has a catalog (the PC) of where each book is located. When a book's location is identified, the librarian fetches that book from the shelf (using the MAR) and places it on the reading desk (the IR). The librarian then knows which book to read or return (execute the instruction) based on that item.

In each cycle, the fetch and execute process consists of clock ticks (t1, t2, t3, etc.). During t1, the address is placed in the MAR, during t2, the instruction is fetched, and during t3, it is moved to the IR. Subsequently, execution of the instruction occurs in a similar sequence of steps.

The entire fetch and execute cycle operates in time cycles, or clock ticks. For instance, t1 refers to the time when the MAR receives the address from the PC, t2 is when the instruction is fetched from memory, and t3 indicates the instruction has reached the IR. This similar timing structure repeats for executing the instruction retrieved, allowing for organized and systematic processing of commands.

Think of this as a relay race. In the race, each runner (clock tick) has a specific task: the first runner fetches the baton (address transfer), the second runner celebrates a completed lap (instruction fetched), and the last runner executes the final sprint (instruction executed). This organized progression helps ensure the race happens efficiently and effectively.

For example, when executing the instruction 1940, the processor fetches it and determines that it means to load a value from a specific memory location into the Accumulator register. The execution will follow specific steps, such as loading the value into the Accumulator from a defined memory address.

In this instruction execution scenario, the instruction '1940' signifies a specific task, such as to load a value into the Accumulator. After fetching this instruction, the system must execute it by identifying the memory address indicated (940), retrieving the data, and then inserting that data into the Accumulator register for use in subsequent operations.

Imagine needing to grab an ingredient from a storage cupboard while cooking (the instruction '1940'). You realize that you need sugar, and you fetch it from the cupboard (memory). Once you have the sugar in your hand (in Accumulator), you can use it in your recipe, similar to how the CPU uses the value in the Accumulator for further calculations.

The instruction format consists of an opcode and operand. The opcode specifies the operation (e.g., load, add), while the operand denotes the memory location or value involved. For instance, '5' might indicate an add operation, whereas '941' specifies the memory address to be used.

An instruction typically includes an opcode and an operand. The opcode informs the CPU what action to perform, such as adding or loading data, while the operand identifies the specific data or location upon which to perform that action. In this way, the CPU can interpret and execute complex operations in a straightforward format.

Consider this as a delivery order. The opcode is the delivery type (e.g., ‘deliver’ or ‘pick up’), while the operand is the delivery address (where the item should go or come from). Just like a courier follows these instructions to manage their deliveries, the CPU relies on this format to understand and execute commands effectively.

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