12.1.7. Resource Conflicts and Clock Cycle Sequence

Now, basically what we are going to do in a fetch cycle. So, it is a fetching and information from memory to the processor. Now, what we must know when we are going to fetch an instruction, at least we have to know the memory location where we have the instruction.

The fetch cycle is the initial stage where the processor retrieves an instruction from memory. To fetch an instruction, it must know the exact memory location of that instruction. This is facilitated by the Program Counter (PC), a special purpose register that holds the address of the next instruction in memory that needs to be fetched.

Think of the fetch cycle like a librarian finding a specific book in a library. The librarian needs to know the exact location of the book, just as the processor needs to know the memory address of the instruction it is going to execute.

So, we are having a special purpose register are called program counter, 𝑃𝐶 - program counter. So, in that particular case, what will happen I am having a call register called program counter, and program counter will have the address of this particular memory location.

The Program Counter (PC) plays a crucial role in instruction fetching. It keeps track of the address of the instruction currently being executed. After fetching an instruction, the PC is typically incremented to point to the next instruction, ensuring a sequential flow of instruction execution.

Imagine the Program Counter as a movie director who knows which scene comes next in a film. After filming a scene (executing an instruction), the director moves to the next scene (increments the PC) to keep the movie rolling smoothly.

First it is going to have the address of an instruction processor fetch this information from memory to the processor, and along with that it will increment 𝑃𝐶 because after completion of this particular instruction, what will happen we have to go to fetch of the next instruction.

Once an instruction has been fetched, the processor needs to update the Program Counter to prepare for the next fetch in the sequence. Incrementing the PC is essential for maintaining the orderly execution of instructions as they are laid out in memory.

If we relate it to reading a book, after reading one page (executing the current instruction), you naturally turn to the next page (increment the PC) to continue the story.

Once we have the instruction in the instruction register, then processor will be knowing what operation we need to perform.

After fetching an instruction, that instruction is stored in the Instruction Register (IR). The IR holds the current instruction that the processor needs to execute. Knowing the instruction allows the Control Unit to understand what actions need to be carried out next.

This is like a chef reading a recipe before cooking. The instruction register is the chef's recipe book, which tells them the specific steps to follow for preparing a dish.

So, after getting the instruction, we know that we have to perform say addition operation, then processor is going to perform the required actions; that means, control unit is going to generate the correct signal at correct time, so that operation can be performed in correct way.

Once the instruction is loaded into the Instruction Register, the Control Unit interprets the instruction and generates control signals that guide the processor's operations, ensuring that tasks are executed in the proper sequence and at the correct time.

Think of the Control Unit as a concert conductor. Just as a conductor signals musicians when to play and how to coordinate their efforts, the Control Unit directs different parts of the processor to work together to complete the instructed operation.

Again we are having two special purpose register, one is known as 𝑀𝐴𝑅 - memory address register, and second one is your 𝑀𝐵𝑅 - memory buffer register.

The Memory Address Register (MAR) holds the address of the memory location to be accessed, while the Memory Buffer Register (MBR) temporarily holds the data being transferred to or from memory. These registers facilitate interaction between the CPU and memory, acting as intermediaries.

You can think of the MAR and MBR like a delivery service. The MAR is the address label indicating where the package (data) should go, and the MBR is the package itself that is either being sent or received.

there are some conflicts, some resource conflict that’s why everything cannot be done in one clock cycle we have to perform in different step.

Resource conflicts occur when multiple operations compete for the same resources at the same time, leading to delays. To manage these conflicts, operations must be carefully sequenced across consecutive clock cycles. This ensures that each operation gets the necessary time and resources it requires without interference from others.

Imagine a busy restaurant kitchen where several chefs need to use the oven. If all chefs try to use it at the same time, chaos ensues. Instead, they take turns using the oven, much like how the processor manages its operations in different clock cycles to avoid conflicts.

In the execution cycle, we are going to perform those operation. So, this information will basically go as an input to your control unit.

During the execution cycle, the processor carries out the operations determined by the instructions in the IR. The Control Unit plays a pivotal role by outputting specific control signals to activate various components of the processor needed for the task at hand.

This can be likened to a project manager delegating tasks to team members. Once the goals are set (instructions are read), the project manager communicates (sends control signals) to the team what tasks to accomplish.

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