19.3.1. Optimizing Finite State Machines

(Refer Slide Time: 19:48) So, first let us take an example called ADD R1,M that is you are taking the memory location value R1 dumping it to R1 after adding it to whatever the content in R1. If you look forget about last class we have discussed that these are the series of control instructions, what are the signals involved? Program counter in, program counter out, Z, MFC all the signals whichever we are listed here are actually utilized for this micro-instruction, sorry; the micro-instructions which will be involved in this macro instructions.

This chunk introduces an example of a basic assembly instruction called 'ADD R1, M', which represents adding a value from a specific memory address (denoted as M) to a register (denoted as R1). The chunk emphasizes that this operation involves a series of control signals essential for executing the instruction. Understanding these control signals—like program counter (PC), MFC (Memory Function Complete), and Z (which likely represents a zero flag or output from an arithmetic operation)—is crucial for grasping how the instruction will be processed by the finite state machine.

Consider a shop cashier who needs to add the price of a new item to the current total on the register. The 'ADD R1, M' operation can be likened to the cashier reading the price from a tag (memory), calculating the new total (register R1), and updating the total amount in the register. The flow of the cash register updates corresponds to the flow of control signals in the state machine for this operation.

So, all these like PC, MAR, read, select 0, ADD, Z they are control signals which you have to generate and then WFMFC is something on which you have to wait till you can go to the third stage. Similarly from the 5th stage to go to the 6th stage basically you have to again wait for the WFMFC; that means, this round this special these two are basically inputs on which the movement of the finite state machine will depend and all other signals are basically being generated which has to be generated by your hardware control unit which in this case is a finite state machine.

This chunk details specific control signals necessary for the execution of the instruction. Control signals like PC (Program Counter), MAR (Memory Address Register), and others like read and select values are crucial to ensuring that the finite state machine operates correctly. The chunk highlights that certain signals must be 'waited upon,' specifically the WFMFC signal, indicating the need for synchronization with hardware conditions. This waiting is essential for moving from one stage of the instruction to another, emphasizing the sequential nature of instruction execution in a finite state machine.

Think of a traffic light system directing cars at an intersection. Just like a traffic light changes signals to manage when cars can move (green=go, red=stop), control signals dictate the flow and operation within a finite state machine. The WFMFC signal serves as a 'green light' for the next stage of instruction execution, ensuring all necessary conditions are met before continuing, similar to how drivers must wait for the green light before proceeding.

So, let us assume that this ADD R1,M whatever may be the opcode for this corresponds to first instruction. So, what is going to happen INS will be 1; that in the decoder the first line will be 1 which corresponds to this instruction which is the first instructions, so whenever the INS is 1, because it’s a decoder. So, only one line will be 1. So, only this finite state machine will be invoked.

This chunk explains how the instruction decoder functions in conjunction with the finite state machine. The instruction's opcode, represented in the decoder as 'INS', determines when a specific finite state machine is activated. When the decoder recognizes the opcode corresponding to 'ADD R1, M', it sets the INS signal to 1, effectively 'activating' the state machine that handles this instruction, which is a key aspect of fine control over instruction processing.

Imagine a vending machine where inserting a specific coin triggers a particular item to be dispensed. The instruction decoder functions similarly—it recognizes the 'coin' (opcode) and allows the corresponding 'item' (state machine) to be accessed and executed. Just as a vending machine can only provide one item at a time based on the specific coin inserted, a finite state machine processes one instruction at a time based on the opcode recognized by the instruction decoder.

So, what is the next state? Next I am going to go to state 1. So, what is the output? Initial state is there from state 0 to state 1 what happens basically, you should know that now I should be in state T that is from 0 next state has come that is counter has now become one. Then what are the outs if you remember there is only one thing over here after initial state basically you need not depend on any other input only thing is that state 1 corresponds to the fact that at present the instruction is INS that is ADD R1,M register to memory.

In this part, the focus is on how the finite state machine transitions from one state to another. Starting from an initial state (state 0), the machine moves to state 1, indicating that the instruction in question (ADD R1, M) is being processed. The explanation indicates that, once in state 1, there are no further inputs needed beyond acknowledging the execution of this instruction, showcasing a straightforward state transition.

Consider a student following steps to complete an assignment. The transition from one step (research) to the next (writing) occurs without needing additional instructions once they understand what to do next. Thus, in this analogy, the student smoothly transitions from state 0 (researching) to state 1 (writing) as they understand what is required to complete that part of the task, similar to how the finite state machine moves through its states.

So, now we have to put it in PC that now PC is updated. Now, we have to it’s important we are waiting for an external signal this is an external signal. So, this is an external signal. So, we have to wait for the external signal only once when it is ready in stage three basically what you can do? The instruction which is now in MDR can be loaded to register in and similarly you can go ahead.

This chunk highlights the importance of external signals in the operation of the finite state machine. Once the program counter (PC) is updated with the new value, the finite state machine must wait for an external signal before proceeding to load the instruction from the Memory Data Register (MDR) into the next register. This waiting for external signals emphasizes the interaction between the finite state machine and the rest of the system, particularly the memory.

Think of a chef waiting for the oven to signal that the food is perfectly cooked before serving it. The finite state machine, like the chef, cannot proceed until it receives that 'ready' signal from the oven (the external signal). Only when the machine confirms that it can safely proceed does it continue with the next step, ensuring perfect operation and timing.

Finally, END = 1 means you have to stop this set of micro-instructions and the macro instruction is over. So, what is to be emphasized it’s very easy to understand only some clocks are there first is this machine is invoked that is the initial state condition enabling is INS that is based on the opcode only when the signal is one you can go to the corresponding state machine.

The concluding part of the instruction processing is discussed here, where the execution reaches an END state, indicating completion of the macro instruction (ADD R1, M). The importance of clock cycles as triggers for state transitions is emphasized, reiterating that the finite state machine executes based on the initial signal (INS) set by decoding the opcode. This focus on timing and control signals is crucial for understanding how instructions are managed in computing.

Imagine a train journey where each station (state) must be reached in order. The train adheres to a schedule (clock), stopping at each predefined station. Reaching the final station signifies that the journey is complete, just like reaching the END state in the finite state machine indicates that all instructions have been executed and no further action is required, wrapping up the process.

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