The basic ideas behind the development of the advanced low-power Schottky TTL (ALS-TTL) and advanced Schottky TTL (AS-TTL) discussed in Section 5.3.8 were further to improve both speed and power consumption performance of the low-power Schottky TTL and Schottky TTL families respectively. In the TTL subfamilies discussed so far, we have seen that different subfamilies achieved improved speed at the expense of increased power consumption, or vice versa. For example, the low-power TTL offered lower power consumption over standard TTL at the cost of reduced speed. The high-power TTL, on the other hand, offered improved speed over the standard TTL at the expense of increased power consumption. ALS-TTL and AS-TTL incorporate certain new circuit design features and fabrication technologies to achieve improvement of both parameters. Both ALS-TTL and AS-TTL offer an improvement in speed–power product respectively over LS-TTL and S-TTL by a factor of 4.

Salient features of ALS-TTL and AS-TTL include the following:
1. All saturating transistors are clamped by using Schottky diodes.
2. Inputs and outputs are clamped by Schottky diodes to limit the negative-going excursions.
3. Both ALS-TTL and AS-TTL use ion implantation rather than a diffusion process, which allows the use of small geometries leading to smaller parasitic capacitances and hence reduced switching times.
4. Both ALS-TTL and AS-TTL use oxide isolation rather than junction isolation between transistors, which leads to reduced epitaxial layer–substrate capacitance, further reducing switching times.
5. Both ALS-TTL and AS-TTL offer improved input threshold voltage and reduced low-level input current.
6. Both ALS-TTL and AS-TTL feature active turn-off of the LOW-level output transistor, producing a better HIGH-level output voltage and thus a higher HIGH-level noise immunity.

Figure 5.21 shows the internal schematic of an advanced low-power Schottky TTL NAND gate. The circuit shown is that of one of the four gates inside a quad two-input NAND (type 74ALS00 or 54ALS00). The multi-emitter input transistor is replaced by two PNP transistors Q1A and Q1B. Diodes D1A and D1B provide input clamping to negative excursions. Buffering offered by Q1A or Q1B and Q2 reduces the LOW-level input current by a factor of (1 + h_FE of Q1A). HIGH-level output voltage is determined primarily by V_CC, transistors Q6 and Q7 and resistors R4 and R7 and is typically (V_CC - 2). LOW-level output voltage is determined by the turn-on characteristics of Q5. Transistor Q2 provides active turn-off for Q4.

Characteristic features of this family are summarized as follows:
- V_IH = 2V; V_IL = 0.8V; I_IH = 20 µA; I_IL = 0.1mA; V_OH = (V_CC - 2)V; V_OL = 0.5V; I_OH = 0.4mA; I_OL = 8mA (74ALS) and 4mA (54ALS);
- V_CC = 4.5–5.5 V; propagation delay (for a load resistance of 500 Ω, a load capacitance of 50pF, V_CC = 4.5–5.5V and an ambient temperature of minimum to maximum) = 11ns/16ns (max.) for LOW-to-HIGH and 8ns/13ns for HIGH-to-LOW output transitions (74ALS/54ALS);
- worst-case noise margin = 0.3V; fan-out = 20; I_CCH (for all four gates) = 0.85mA; I_CCL (for all four gates) = 3mA;
- operating temperature range = 0–70°C (74-series) and −55 to +125°C (54-series); speed–power product = 4.8pJ; maximum flip-flop toggle frequency = 70MHz.