OR/NOR is the fundamental logic gate of the ECL family. Figure 5.32 shows a typical internal schematic of an OR/NOR gate in the 10K-series MECL family. The circuit in essence comprises a differential amplifier input circuit with one side of the differential pair having multiple transistors depending upon the number of inputs to the gate, a voltage-and-temperature-compensated bias network and emitter follower outputs. The internal schematic of the 10H-series gate is similar, except that the bias network is replaced with a voltage regulator circuit and the source resistor R of the differential amplifier is replaced with a constant current source.

Typical values of power supply voltages are V = 0 and V =−5.2 V. The nominal logic levels are logic LOW=logic ‘0’=−1.75 V and logic HIGH=logic ‘1’=−0.9V, assuming a positive logic system. The circuit functions as follows. The bias network configured around transistor Q produces a voltage of typically −1.29V at its emitter terminal. This leads to a voltage of −2.09V at the junction of all emitter terminals of various transistors in the differential amplifier, assuming 0.8V to be the required forward-biased P–N junction voltage.

Now, let us assume that all inputs are in a logic ‘0’ state, that is, the voltage at the base terminals of various input transistors is −1.75V. This means that the transistors Q1, Q2, Q3, and Q4 will remain in cut-off as their base-emitter junctions are not forward biased by the required voltage. This leads us to say that transistor Q7 is conducting, producing a logic ‘0’ output, and transistor Q8 is in cut-off, producing a logic ‘1’ output.

In the next step, let us see what happens if any one or all of the inputs are driven to logic ‘1’ status, that is, a nominal voltage of −0.9V is applied to the inputs. The base-emitter voltage differential of transistors Q1–Q4 exceeds the required forward-biasing threshold, with the result that these transistors start conducting. This leads to a rise in voltage at the common-emitter terminal, which now becomes approximately −1.7V as the common-emitter terminal is now 0.8V more negative than the base-terminal voltage.

This explains how this basic schematic functions as an OR/NOR gate. We will note that the differential action of the switching transistors (where one section is ON while the other is OFF) leads to simultaneous availability of complementary signals at the output. Figure 5.33 shows the circuit symbol and switching characteristics of this basic ECL gate.

It may be mentioned here that positive ECL (called PECL) devices operating at +5V and ground are also available. When used in PECL mode, ECL devices must have their input/output DC parameters adjusted for proper operation. PECL DC parameters can be computed by adding ECL levels to the new VCC.

We will also note that voltage changes in ECL are small, largely governed by VBE of the various conducting transistors. In fact, the magnitude of the currents flowing through various conducting transistors is of greater relevance to the operation of the ECL circuits. It is for this reason that emitter coupled logic is also sometimes called current model logic (CML).