PROGRAMS TO BE EXECUTED - 4 | EXPERIMENT NO. 5 TITLE: Interrupt Handling and Timer Interfacing (8085/8086 Microprocessors with 8253/8254 Timer) | Microcontroller Lab
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Interactive Audio Lesson

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Introduction to Interrupts

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0:00
Teacher
Teacher

Let's start by understanding what interrupts are. Can anyone tell me their significance in microprocessor-based systems?

Student 1
Student 1

Interrupts allow the CPU to pause its current task to handle important events, right?

Teacher
Teacher

Yes, exactly! They enable event-driven processing, which is crucial for efficient CPU usage. What about the difference between hardware and software interrupts?

Student 2
Student 2

Hardware interrupts come from external devices, while software interrupts are generated by program instructions.

Teacher
Teacher

That's correct! Remember the acronym 'HS' for Hardware and Software to keep them distinct. Now, let's summarize: interrupts allow for efficient CPU utilization by responding to external or internal signals.

Handling RST 7.5 in 8085

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0:00
Teacher
Teacher

Now that we understand interrupts, let's dive into RST 7.5 on the 8085. Who can explain how we configure it?

Student 3
Student 3

We need to set up the 8255 to output to an LED and then write an ISR starting at the vector address 003CH.

Student 1
Student 1

And we must remember to use the SIM instruction to enable the interrupt!

Teacher
Teacher

Exactly! The SIM instruction is crucial. It can reset pending interrupts and allow for selecting which interrupts to mask. Let’s summarize: setup involves configuring the I/O and writing the ISR where the LED toggling occurs.

Timer Interfacing

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0:00
Teacher
Teacher

Moving forward, let's explore timer interfacing with the 8254. What are some key features of this timer?

Student 2
Student 2

It has three independent 16-bit counters and can generate precise timing signals.

Student 4
Student 4

It can be programmed for different modes, like generating square waves or delays!

Teacher
Teacher

Great observations! Remember the modes: Mode 0 is for one-shot delays, while Mode 3 generates a square wave. Let's summarize the importance of understanding these timers in embedded systems.

Introduction & Overview

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Quick Overview

This section elaborates on the programs required for understanding interrupt handling and timer interfacing in microprocessors, focusing on 8085 and 8086 architectures.

Standard

In this section, we explore two programs related to interrupt handling using RST 7.5 and timer interfacing using the 8254 timer. The details cover the structure of assembly language code, expected outcomes, and the significance of each component used in hardware interfacing with microprocessors.

Detailed

Overview of Programs to be Executed

This section highlights the practical implementations required for understanding microcontroller operations, particularly focusing on interrupts and timer usage.

Programs on Interrupt Handling

The first program demonstrates how to configure the 8085 microprocessor to respond to hardware interrupts using the RST 7.5 signal. It enables students to observe interactive behavior, specifically toggling an LED through an interrupt service routine (ISR). The program consists of initialization, interrupt enabling, and the ISR to handle LED toggling, with specific memory instructions mapped out. The outcomes yield direct observations of how interrupts facilitate real-time processing and event handling.

Timer Interfacing Programs

The second program illustrates interfacing with the 8254 Programmable Interval Timer to generate controlled delays and square waves. By configuring the timer to operate in different modes (such as Mode 0 for one-shot pulsing and Mode 3 for continuous square wave generation), students will gain practical experience observing LED states and understanding timer functionality. The assembly code outlines control word configurations and execution strategies to achieve desired temporal outputs, fostering a deeper grasp of lower-level programming in real-time systems.

In summary, this section not only provides hands-on programming experiences but also contextualizes their relevance in hardware design and embedded systems.

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Part A: Interrupt Handling (8085)

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Assume 8085 I/O addresses for 8255 (Port A=80H, CWR=83H) and 8254 (Counter 0=90H, CWR=93H).

Program A.1: Toggle LED via RST 7.5 Interrupt
Objective: To configure an 8085 system such that an RST 7.5 hardware interrupt toggles the state of an LED connected to 8255 Port A, bit 0.

Assumption: LED connected to 8255 Port A, bit 0 (PA0). 8255 Port A configured as output.

Control Word for 8255 (Port A = Output):
- D7=1 (I/O Mode), D6,D5=00 (Mode 0), D4=0 (PA=Out), D3=1 (PCU=In), D2=0 (Mode 0), D1=1 (PB=In), D0=1 (PCL=In)
- Resulting Control Word: 10001111b = 8FH

Assembly Code:

; Main Program - Configures 8255, Enables Interrupts
; Starting Address: 2000H
ORG 2000H
START:
MVI A, 8FH ; Configure 8255: Port A as Output
OUT 83H ; Write to 8255 CWR
MVI A, 00H ; Initialize LED to OFF (PA0 = 0)
OUT 80H ; Output to Port A
MVI A, 18H ; Enable RST 7.5 interrupt (SIM byte: D4=1 to reset pending, D3=1 for MSE, D2=0 to unmask 7.5)
SIM ; Set Interrupt Mask
EI ; Enable Global Interrupts
LOOP: JMP LOOP ; Infinite loop, waiting for interrupt

; --- Interrupt Service Routine (ISR) for RST 7.5 ---
; This routine is automatically called when RST 7.5 occurs.
ORG 003CH ; ISR should ideally be placed here
ISR_RST7_5:
PUSH PSW ; Save Accumulator and Flag Register
PUSH B ; Save BC pair (if used)
PUSH D ; Save DE pair (if used)
PUSH H ; Save HL pair (if used)
IN 80H ; Read current state of Port A into Accumulator
XRI 01H ; Toggle bit 0 (00000001b). If PA0 was 0, it becomes 1; if 1, it becomes 0.
OUT 80H ; Output the new state back to Port A
MVI A, 18H ; Re-enable RST 7.5 by resetting its pending flip-flop
SIM ; (D4=1 for R7.5, D3=1 for MSE, D2=0 for M7.5)
POP H ; Restore HL pair
POP D ; Restore DE pair
POP B ; Restore BC pair
POP PSW ; Restore Accumulator and Flag Register
EI ; Re-enable global interrupts before returning (important for nested interrupts)
RET ; Return from Interrupt to the main program

Memory Layout (Example, depends on trainer kit's initial memory state):
- Main Program (Starting at 2000H):
| Address | Hex Code | Instruction / Operand |
| :------ | :------- | :-------------------- |
| 2000H | 3E | MVI A |
| 2001H | 8F | (Operand) |
| 2002H | D3 | OUT |
| 2003H | 83 | (Operand) |
| 2004H | 3E | MVI A |
| 2005H | 00 | (Operand) |
| 2006H | D3 | OUT |
| 2007H | 80 | (Operand) |
| 2008H | 3E | MVI A |
| 2009H | 18 | (Operand) |
| 200AH | 30 | SIM |
| 200BH | FB | EI |
| 200CH | C3 | JMP |
| 200DH | 0C | (Operand - LSB) |
| 200EH | 20 | (Operand - MSB) |

  • ISR (Starting at 003CH):
    | Address | Hex Code | Instruction / Operand |
    | :------ | :------- | :-------------------- |
    | 003CH | F5 | PUSH PSW |
    | 003DH | C5 | PUSH B |
    | 003EH | D5 | PUSH D |
    | 003FH | E5 | PUSH H |
    | 0040H | DB | IN |
    | 0041H | 80 | (Operand) |
    | 0042H | EE | XRI |
    | 0043H | 01 | (Operand) |
    | 0044H | D3 | OUT |
    | 0045H | 80 | (Operand) |
    | 0046H | 3E | MVI A |
    | 0047H | 18 | (Operand) |
    | 0048H | 30 | SIM |
    | 0049H | E1 | POP H |
    | 004AH | D1 | POP D |
    | 004BH | C1 | POP B |
    | 004CH | F1 | POP PSW |
    | 004DH | FB | EI |
    | 004EH | C9 | RET |

Expected Outcomes:
- Initially, the LED connected to PA0 will be OFF.
- Upon pressing the RST 7.5 button, the LED should turn ON.
- Upon pressing the RST 7.5 button again, the LED should turn OFF.
- This toggling behavior should continue with each subsequent interrupt.

Detailed Explanation

In this part of the program, we configure the 8085 to handle an RST 7.5 interrupt. The goal is to make an LED connected to the microprocessor toggle its state every time the interrupt occurs. The program first sets up the 8255 to connect the LED as an output. It then enables the RST 7.5 interrupt by configuring the interrupt mask and eventually loops waiting for that interrupt. Upon the interrupt activation, the ISR is executed, which toggles the LED's state before returning control back to the main program.

Examples & Analogies

Think of this process like a light switch where every time a doorbell rings (the interrupt), instead of getting up to manually turn on the light, the switch (the microprocessor) automatically toggles the light on or off. The ISR can be imagined as the trained butler who responds instantly to the doorbell.

Definitions & Key Concepts

Learn essential terms and foundational ideas that form the basis of the topic.

Key Concepts

  • Interrupts enable CPUs to efficiently manage multiple tasks by responding to events.

  • RST 7.5 is a specific interrupt in the 8085 processor architecture for handling high-priority tasks.

  • The 8254 timer can operate in multiple modes for various timing applications.

Examples & Real-Life Applications

See how the concepts apply in real-world scenarios to understand their practical implications.

Examples

  • Using RST 7.5 to toggle an LED demonstrates the interrupt's practical application.

  • Programming the 8254 to create a square wave illustrates its flexibility in generating precise timing signals.

Memory Aids

Use mnemonics, acronyms, or visual cues to help remember key information more easily.

🎵 Rhymes Time

  • Interrupts aid the CPU's plan, pausing work to lend a hand!

📖 Fascinating Stories

  • Imagine a postman (the interrupt) that interrupts a chef (the CPU) to deliver an urgent message (the event). The chef quickly checks and resumes cooking!

🧠 Other Memory Gems

  • Remember the acronym RISE: RST 7.5 Interrupts Support Events!

🎯 Super Acronyms

Use HATS for handling interrupts

  • Hardware
  • Active
  • Timer
  • Software.

Flash Cards

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Glossary of Terms

Review the Definitions for terms.

  • Term: Interrupt

    Definition:

    A signal that temporarily halts the current execution of a program to manage events requiring immediate attention.

  • Term: RST 7.5

    Definition:

    A maskable hardware interrupt in the 8085 microprocessor that triggers an ISR.

  • Term: ISR (Interrupt Service Routine)

    Definition:

    A special block of code that handle interrupt requests when an interrupt is acknowledged.

  • Term: 8254 Timer

    Definition:

    A programmable interval timer capable of generating precise time delays and square wave outputs.