6.1. Introduction to RTL Verification

Try these first

1. 1.

   What does RTL stand for?

   Hint

   Think of the level at which the design is verified.

2. 2.

   Name one tool used for functional simulation.

   Hint

   It's a name you may have heard in class.

3. 3.

   What does RTL stand for?

   • Real Transfer Level
   • Register Transfer Level
   • Read-Transfer Level

   Hint

   It's related to how digital designs are organized.

4. 4.

   True or False: Timing simulation checks only the logical correctness of design.

   • True
   • False

   Hint

   Remember the meaning of timing and logical correctness.

5. 5.

   You are tasked with verifying an RTL design using both functional and timing simulation. Describe the steps you would take and how you would set up your testbench for both types.

   Hint

   Think of both what data inputs you need and the timing considerations that must be accounted for.

6. 6.

   Given a fictitious digital design that seems to fail during timing simulation, how would you use assertions to help debug the issue?

   Hint

   Consider what conditions you would want to ensure hold and timing performances.