6.2.1. Functional Simulation

Functional simulation is the most common form of simulation-based verification. It checks whether the design behaves as expected under a set of test inputs.

Functional simulation is a technique used during the design verification process of digital systems. Its primary purpose is to ensure that the design performs the functions it is supposed to under various test conditions. This involves running the RTL code through a simulator that applies predefined inputs to the design and checks whether the resulting outputs match the expected results.

Think of functional simulation like taking a car for a test drive. Before you buy the car, you want to make sure it runs smoothly, accelerates, and stops properly. Just as you would check if the car behaves as expected under different driving conditions, functional simulation checks if the design behaves correctly with various input scenarios.

During functional simulation, the simulator runs the RTL design with a set of predefined testbenches that stimulate the design and check its output.

In functional simulation, a testbench is created to provide inputs to the design (also known as the Design Under Test or DUT). The simulator executes the RTL model with these inputs and compares the outputs against the expected results. The testbench is crucial as it defines the conditions under which the design is tested, which helps in identifying logical errors early in the design process.

Consider the testbench as a cooking recipe. Just as a recipe provides specific steps and ingredients to create a dish, the testbench provides specific inputs to the design to ensure it produces the intended output. If you follow the recipe correctly and the final dish doesn’t taste right, then you know there may be a problem with the recipe (or the cooking process), similar to finding issues in the design when testing with the testbench.

Common tools for functional simulation include ModelSim, VCS (Verilog Compiler Simulator), XSIM, and Questa.

There are various tools available for functional simulation that help designers validate their RTL code. Each tool has unique features but commonly allows designers to run simulations, apply different inputs, and analyze outputs. Tools like ModelSim and VCS are widely recognized in the industry for their efficiency and ease of use.

Using simulation tools is like using different tools for building a piece of furniture. Just as a carpenter might choose a specific saw or drill based on the requirements of the project, engineers select functional simulation tools based on their design needs and the complexity of the systems they are working on.

module testbench;
reg clk, reset;
wire [3:0] out;
// Instantiate the design under test (DUT)
my_design dut (
.clk(clk),
.reset(reset),
.out(out)
);
// Clock generation
always begin
#5 clk = ~clk; // 10 ns clock period
end
// Stimulus generation
initial begin
clk = 0;
reset = 1;
#10 reset = 0; // Reset the DUT for 10 ns
#20 reset = 1; // Apply reset again at 20 ns
#100 $finish; // End simulation after 100 ns
end
endmodule

This Verilog code illustrates a simple functional simulation testbench for a design module called 'my_design'. It sets up a clock signal and a reset signal to simulate how the design operates over time. The simulation runs for a defined period, during which it applies the reset, allowing observers to check if the outputs of 'my_design' behave as expected given these inputs.

Think of this code as a script for a stage play. The 'testbench' defines the roles (clock and reset), the actions that will happen over time (like the reset happening after 10 ns), and how long the performance will last (ending after 100 ns). Each line of the script helps in ensuring that the play (or design) progresses as intended, culminating in a final performance that audiences can evaluate.

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