3.7.1. Basic Testbench Structure

Try these first

1. 1.

   What is the purpose of a testbench in Verilog?

   Hint

   Think about verification methods.

2. 2.

   What signal types would you use for inputs and outputs in a testbench?

   Hint

   Recall the basic signal types in Verilog.

3. 3.

   What is the main purpose of a testbench in Verilog?

   • A) To create the design.
   • B) To validate the DUT.
   • C) To synthesize the design.

   Hint

   Think about the verification process.

4. 4.

   True or False: The testbench can be considered a separate module from the DUT.

   • True
   • False

   Hint

   Look back at the structure of a testbench.

5. 5.

   Create a testbench for a 4-bit adder module. Include clock generation, stimulus for adding numbers, and output monitoring.

   Hint

   Think about how specific inputs will create the expected output.

6. 6.

   Design a testbench that includes error checking for a state machine. Ensure it monitors unexpected states.

   Hint

   Consider how to define valid states and what unexpected values might be.