Memory Access/Write Back Cycle (if needed)

The **Memory Access/Write Back Cycle** is the final phase for instructions that store results. The Control Unit places the target address in MAR, data in MDR, and initiates a memory write for STORE operations. For results destined for CPU registers, the CU enables the transfer of the ALU's output to the specified register. ### Medium Summary The **Memory Access/Write Back Cycle** is the concluding phase in an instruction's execution, occurring only when the computed result needs to be stored, either back into main memory (for `STORE` operations) or into a CPU general-purpose register. For memory writes, the Control Unit (CU) generates control signals to place the target memory address into the Memory Address Register (MAR) and the data to be written into the Memory Data Register (MDR), then initiates a `MEM_WRITE` command. If the result is meant for a general-purpose register, the CU orchestrates the transfer of the ALU's output (or an internal buffer's content) to the designated destination register, ensuring the CPU's state is updated correctly for the next instruction. ### Detailed Summary ### ● Memory Access/Write Back Cycle (if needed): If the instruction is a STORE operation or involves writing a result to memory, the CU generates signals to: * Place the target memory address into the MAR. * Place the data to be written into the MDR. * Initiate a memory write. If the instruction's result needs to be stored in a general-purpose register, the CU generates signals to enable the result's transfer from an internal buffer or ALU output to the specified destination register.