28.1.1. Different Internal CPU Bus Organization

Hello and welcome to the last unit of this module of control unit and here in this unit we will be discussing about different internal CPU bus organization. Throughout this module on control unit, we have seen how we can generate different types of control signals and the types of instructions that involve these control signals. We have discussed how control signals can be generated using hardwired control, followed by micro programmed control units. However, we have assumed a single bus architecture where one bus carries both data and control signals.

In this section, the speaker introduces the topic of internal CPU bus organization and summarizes the content covered in previous modules about control units. The emphasis is on the typical single bus architecture used in CPUs, where a single communication line handles both data and control signals. This introduction sets the context for discussing the potential benefits and disadvantages of incorporating multiple bus architectures in CPU design.

Think of a single bus architecture like a single-lane road where cars (data) and signals (control signals) travel together. There's only one lane, so traffic can become congested, slowing everything down. In contrast, a multi-lane highway can facilitate more cars traveling simultaneously, akin to how multiple buses in a CPU can handle more data and control signals efficiently.

One clear advantage of multiple buses is that they allow operations to be performed in parallel, thereby requiring fewer control steps. More paths lead to faster data processing since multiple operations can occur at the same time. However, more buses come with increased costs in circuit design and chip manufacturing.

The speaker discusses the main advantage of using multiple buses in a CPU: parallel processing. With more buses, the CPU can perform several operations simultaneously, reducing the time required for control steps and overall processing. However, this efficiency comes at a cost, as more buses increase the complexity and expense of the CPU design, involving additional circuits and managing multiple pathways for data.

Imagine you are at a restaurant with multiple waiters (buses) serving tables (operations) at the same time—food (data) can be delivered faster and more efficiently. However, having too many waiters increases the coordination costs and complexity for the restaurant manager (the CPU designer).

To illustrate how multiple bus architectures work, we will focus on a three-bus architecture, comparing it briefly with the single-bus architecture. For example, in a single bus system, adding two numbers would require three steps: first inputting the first number, then the second, and finally storing the result. In a three bus system, this can be done more efficiently in one step.

The speaker introduces the concept of a three-bus architecture, which allows operations to be completed more efficiently compared to a single-bus system. It describes an example of adding two numbers where, in a single bus system, three steps are needed to read the inputs and produce the output. In contrast, a three-bus system can handle the entire operation in a single step due to its ability to process inputs and outputs concurrently.

Think of this scenario like a production assembly line. In a single-bus system (one conveyor belt), each item has to be processed one after the other, taking more time. In a three-bus system (three conveyor belts), several items can be worked on simultaneously, resulting in faster production and efficiency—just like a team working together on multiple tasks simultaneously.

When considering the program counter and registers in a multiple bus architecture, there are some key changes. In a single bus system, updating the program counter involves multiple stages and temporary storage. However, in a three-bus system, the program counter can be updated more directly due to multiple input/output ports, streamlining the process.

The speaker highlights how the design of the program counter and registers will change with a multiple bus architecture. In a single bus architecture, updating the program counter needs several phases to transfer data through temporary storage. With multiple buses, updates happen more smoothly and quickly because inputs and outputs can be processed at the same time, meaning less overall latency in instruction fetching.

Consider a library with a single-checkout desk (single bus) where patrons must line up to check out books one at a time, taking a long time during busy periods. In contrast, a library with multiple checkout desks (three buses) can serve several patrons simultaneously, speeding up the entire process significantly. This illustrates how multiple bus systems can improve the efficiency of operations like updating program counters in CPUs.

--