8.1.2. Instruction Fetching

So, in this fetch stage so, PC is equal to you are keeping the value of the memory address register can I actually merge this 2 in a single time step not possible, because in the first unit the value of the program counter will go to the memory address register, you give some time give one unit of time for that, then the memory address register will be read, now the memory will know that I have to supply the data which is actually the instruction from the address, which is given in the memory address register.

In the instruction fetching stage, the Program Counter (PC) holds the address of the next instruction to be fetched. This address is transferred to the Memory Address Register (MAR) for the actual fetching process. Both operations cannot occur simultaneously because the value needs to be stabilized before the memory can access it. Therefore, the program counter's value is first passed to the MAR, then the MAR is used to get the instruction from memory.

Think of the PC as a librarian who tells the assistant (MAR) which book to fetch. The librarian can't pull the book from the shelf simultaneously; they first need to communicate the book's location, after which the assistant can find and fetch it. This process takes a moment, and the librarian is busy until that instruction is fed to the assistant.

So, if you are free at hand then actually I can reuse the PC that indicates I am incrementing it by one. So, memory, taking the data from the memory to the memory buffer register and program counter increment these 2 micro instructions you can do it in time steps 2, because they are 2 non-dependent micro instructions.

Once the value from the PC is given to the MAR, the PC is no longer required for that operation and can be incremented by one to point to the next instruction. Additionally, the data fetched from memory can be transferred to the Memory Buffer Register (MBR). These two actions can occur in the same time step because they do not depend on each other, allowing for efficient processing.

Imagine the librarian has finished telling the assistant where to find the current book. While the assistant fetches that book, the librarian can jot down the next book's location. Both actions happen simultaneously, making the process quicker.

Of course again I cannot merge step 2 and step 4, because step 2 actually tells that I am bring the data from the location. Before the data is brought to the memory buffer register you cannot directly transfer to the IR.

Some operations depend on the completion of others. For instance, the data retrieval step (step 2) must complete before that data can be stored in the Instruction Register (IR). Therefore, steps that are dependent cannot be combined, which creates a need for proper sequencing in instruction fetching.

It's like cooking a dish where you must boil water before adding pasta. You can't add the pasta until the water is boiling. Similarly, in fetching instructions, you can't move data into the IR until it has been fully retrieved from memory.

So, basically 3 time steps or micro instructions are required or 4 micro instructions are required, but in 3 time steps you can complete the fetch stage.

Clock grouping enables optimizing the instruction fetching stage. Though initially it may seem that up to four micro-instructions are needed, through strategic grouping, it's possible to complete the operation in just three time steps. This is done by combining non-dependent tasks to maximize efficiency during fetching.

Consider a team of workers building a wall. If two workers can perform their tasks simultaneously without reliance on each other, they will complete the work faster than if they had to wait for each other.

Then again you have to load the memory address register with this 3030.

In instruction fetching, there are differences in how immediate and non-immediate addressing modes function. For immediate modes, the operand is available right in the instruction, while for non-immediate modes, like direct addressing, an additional step involves retrieving the operand from a specified memory address.

Think of an immediate mode as a shopping list with all the items written down. You can buy everything directly. In contrast, non-immediate is like checking a locker first (address) to see what you need before you can buy anything, requiring one extra step.

So, what we have seen if you are not going for any clock grouping then the number of time units required to go for a fetch immediate instruction will be 4.

Without clock grouping, the instruction fetching process could take up to four time units for immediate mode instructions. The lack of optimization increases the total duration of processing, emphasizing the importance of efficiently sequencing these operations.

If you go to the grocery store and take one item at a time rather than grabbing several things that are nearby, you'll take longer to complete your shopping. Efficient planning—like clock grouping—saves time.

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