13.2.2. Stage 1: Operand Loading from Registers

Let us again clean it up, because we will have to revisit this figure many times. So, again I am cleaning it up. So, next is what? Now what now actually next stage is till now we have seen, that the output of this 𝑃𝐶 = 𝑃𝐶 + 1 is memory is in register 𝐼𝑅 and memory has you have given the command to read the memory. In second stage what we do? so whatever I told you about the first one is written over here, you can read it now what is it says 𝑍 𝑃𝐶. So now, what 𝑜𝑢𝑡 𝑖𝑛 this 𝐼𝑅 has, if you look at the initial last slide then 𝐼𝑅 had the value of 𝑃𝐶 = 𝑃𝐶 + 1, but at that time it was 𝑍 .

In this step, we clarify the previous actions where the Program Counter (PC) has been incremented and its value is stored in the Instruction Register (IR). This IR now holds the command to read from memory, indicating that the next stage is about fetching the actual instruction from memory into the IR. The term 𝑍 𝑃𝐶 refers to how the values are moved through the system, with 'Z' representing perhaps a status or flag related to the operation.

Think of a library where you first note down the number of a book on a piece of paper (the Program Counter), and after writing the number down, you go look for that book (the read command). Just as you fetch that book, the system fetches the instruction stored in memory.

So now, I am making as 𝑍 and 𝑃𝐶; that means, the value of 𝐼𝑅 will go to 𝑃𝐶 program counter, via the bus because 𝑍 and 𝑃𝐶 and we are waiting for 𝑊𝐹𝑀𝐶 so are waiting till the memory out says that, I am ready and whatever you asked in the first stage it has been dumped to the memory buffer register.

Here, we are preparing to load the instruction retrieved from memory into the Instruction Register (IR). The value fetched is indicated by 𝑍, which carries the instruction over to the program counter (PC). We also have to wait for a signal (WFMC) that indicates whether the memory is ready to send out its data. This illustrates the synchronization required between different components in a CPU.

Imagine waiting for the librarian to confirm that the book you've requested is ready for pickup. Only once you have the confirmation do you proceed to collect the book. Similarly, the system waits for the memory to confirm it's ready before loading the instruction.

Then after, once the memory is ready, you have to load it into load it, load the value of this instruction into the instruction register, very simple you will make memory data register out and register in. So now, your instruction is over here, you have to load it to the instruction register.

In this stage, after the memory has confirmed it's ready, the instruction will be moved from the Memory Data Register (MDR) into the Instruction Register (IR). The MDR acts as a temporary holding area for data read from memory until that data is transferred to the IR which is critical for executing operations. This is where the CPU takes a significant step towards actually performing the commanded operation.

This can be compared to receiving a package (the instruction) that you ordered online. When the package arrives, you take it from the delivery person (MDR) and open it to read the contents (IR), which informs you what to do next.

Now, what is your instruction, that is 1, 2 and 3 will be the same for all instructions, you know that is instruction fetch. Now instruction has been fetched, it is in the instruction register now you have to tell what I have to do. So, what was the instruction the instruction was basically, load 𝑅1, 𝑀 that is whatever is present in the memory location that is 𝐿𝑂𝐴𝐷 𝑅1, 𝑀; that means, in memory location 𝑀 whatever value is, there data is there you have to load it into 𝑅1.

This segment emphasizes that after fetching the instruction and placing it in the IR, the next vital step is to decode what action is required. For this instruction type, it indicates loading data from a specified memory location (M) into a register R1. This decoding step is critical as it informs the control unit about what operations need to be conducted next.

You can think of this like a computer receiving a command to open a specific file. In this case, the command is decoded to understand which file (memory location M) to access and what action (load into R1) to perform with it.

So now, what? So, you have to take this value 𝑀 and loaded it into the memory address register, because that part is going to tell where the operand exists so obviously, first instruction will be 𝐼𝑅 because the value of the instruction, which is present in the instruction register has to be given into the bus, and then your memory address register basically, we read the value from 𝑀.

Here, we're focusing on how the memory address register (MAR) is used to specify the location from which data will be read. The instruction in the IR indicates the memory location we need to interact with - in this case, the address specified by M. This step is crucial for guiding the CPU on where to access data from memory.

This could be likened to using a map to find a particular shop in a city. The MAR is like the map, telling the CPU precisely where to go in the vast area of memory to retrieve the necessary data.

So now, what happens? Now the memory is ready, now what you have to do you have to load it into load it, load the value of this instruction into the instruction register, very simple name memory data register out and register in as simple as that just have a very quick look. So now, your instruction is over here, you have to load it to the instruction register.

After the MAR specifies the correct location, the CPU waits for the memory to provide the data from that address. Once received, that data will be loaded into R1. This explains the final step for completing the instruction fetch and prepare for execution.

Finally, once you know where the shop is (the memory address), you walk in and retrieve the item you wanted. In the microprocessor, the memory retrieves the required data and hands it over to the designated register (R1) for processing.

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