29.1.2. Data Flow in Three Bus Architecture

Of course; similar because we are not handling multiple instructions. So, ALU can do only one operation at a time.

This section introduces the concept of a three bus architecture, highlighting its main characteristic: handling one operation at a time through the ALU (Arithmetic Logic Unit). In simpler terms, the ALU is responsible for performing calculations but can only work on one instruction or data set at any given point, emphasizing a sequential processing model.

Think of the ALU like a chef cooking in a kitchen. The chef can only prepare one dish at a time, focusing on that dish until it's ready, before moving on to the next. Just like this, the ALU can only work on one task at a time.

So, as I told you if you remember if it’s a single bus architecture then first the data comes here and gets stored in a temporary variable. Second stage this value gets directly fed over here the addition or subtraction is done, and the output is also stored in a temporary register.

In a single bus architecture, the process begins with data input, which gets stored temporarily for processing. The next step involves performing calculations like addition or subtraction with that stored data. After the operation, the result is also saved temporarily. This process requires multiple stages because there is only one bus available to handle data transfer.

Imagine you are baking cookies. First, you gather all ingredients (data) and set them aside (temporary variable). Then, you mix them together (perform operation), and once mixed, you put the cookie dough back into a bowl (temporary register) before putting it in the oven. Each action must wait for the previous one to finish.

But if you look at if there are multiple registers multiples wires, then actually all these things all these temporary registers can be done away.

The section highlights a significant advantage of the three bus architecture. With multiple registers and connections (wires), there is a drastic reduction in the need for temporary storage. This increase in bus availability allows for simultaneous data transfers and simplifies the overall architecture by eliminating extra temporary registers.

Think of a fast-food restaurant's assembly line. If there are multiple workers at various stations (buses), they can handle different tasks simultaneously without waiting for others. In contrast, if only one worker is available (single bus), everything slows down as tasks must wait their turn.

So, again I will first show you that is the three bus architecture, we have three buses A, B and C and these are the internal components like PC, register, ALU, decoder, instruction register etcetera. But now we will try to assume here that bus A and B if you look at it, bus A and B are going to take the data from the output of the registers and blocks and bus C mainly basically is going to take the data and write it to the registers.

This part describes the three buses in the architecture: A, B, and C. Buses A and B are utilized to take data from different components (like registers) to be processed. Bus C, on the other hand, is responsible for writing the processed data back to the registers. This clear segregation of roles among the buses enhances the efficiency of data processing.

Consider a factory with three conveyor belts (buses). Conveyors A and B transport raw materials (data) to the assembly line, while conveyor C takes the completed products (processed data) back to storage. Each conveyor has a specific role, making the whole process faster and more efficient.

ALU is slightly different. So, in the in all other cases basically the registers they are going to dump the values to A and B and read from C, but ALU is slightly reverse they will take the values from A and B and the output will dump to C.

This section explains the operations of the ALU in the context of a three bus architecture. Unlike other components that send data to buses A and B from which they retrieve processed data, the ALU takes its inputs from buses A and B for computation and sends the result out through bus C. This reverse dynamics shows the unique function of the ALU within the architecture.

Think of the ALU as a blender in a kitchen. You add ingredients (inputs) into the blender (between buses A and B), then when you blend them, the smoothie (output) is dispensed from the spout (bus C). The blender accepts ingredients from above and dispenses the final product down below.

Again this is very similar to the single bus concept mux with a select it is a constant, then program counter will be incremented, otherwise it is going to take the operand from bus A. Bus second operand B is directly connected to the ALU.

This part discusses how the registers operate within the three bus architecture. The multiplexing concept (mux) is used in controlling data flow, with the program counter being able to be incremented or select operands from bus A for operations. Additionally, the second operand is directly linked to the ALU, facilitating faster data access.

Think of a remote control for your television. You can either change the channel (increment the program counter) or directly select a show (select operand from bus A) without waiting. This direct access saves time and enhances functionality.

Memory data register it has four ports, it dumps the value to two register two lines A and B takes the input from line numbers C and also it can the bidirectional bus if you see it goes to the memory.

In discussing the memory data register (MDR), the text explains that it now features four ports. This improvement allows the MDR to send data to two different outputs simultaneously while also receiving input through another line, enhancing the bidirectional communication with memory components.

Picture an advanced library system with multiple check-out desks (ports). Books (data) can be checked out at two desks at the same time, while returns can be processed on another desk, allowing library members to access resources more efficiently.

--