29.1. Three Bus Architecture

Of course; similar because we are not handling multiple instructions. So, ALU can do only one operation at a time. So, ALU just like this if you look at it, it is something like this and something like this. You cannot there is no means point in putting multiple input output ports and because we are actually not going to handle multiple instructions, but one actually changes here, this is something interesting.

In the Three Bus Architecture, the Arithmetic Logic Unit (ALU) processes one operation at a time rather than handling multiple instructions simultaneously. This means that it is designed to perform tasks in a sequential manner. The design is focused on ensuring that the ALU works efficiently for the tasks it needs to perform, as opposed to accommodating multiple instructions at once, which would complicate the architecture.

Consider a chef in a kitchen who can only cook one dish at a time. Although the chef has all the ingredients and tools available, they must focus on one recipe until it's completed before starting another. This ensures that each dish is prepared properly without confusion.

So, as I told you if you remember if it’s a single bus architecture then first the data comes here and gets stored in a temporary variable. Second stage this value gets directly fed over here the addition or subtraction is done, and the output is also stored in a temporary register. And then in the third phase this one will go over there this one will be erased the erase means it is nullified, and the value will travel to the bus and go to the register.

In a single bus architecture, data must go through various stages: it enters, is temporarily stored, processed, and then stored again before moving to its final location. This process requires temporary registers for staging the data, which can slow down operations. In contrast, a three bus architecture streamlines this process by allowing data to move more freely between components without the need for many temporary storage points.

Imagine a factory assembly line where each part must wait at a station before moving to the next. A single line requires each part to stop at multiple stations (like temporary registers) before reaching its final destination. In a more efficient assembly line with multiple paths (like three buses), parts can move more quickly and directly to where they are needed, reducing wait times.

So, what are the basic objectives of the unit, the basic objective of the unit is one is a comprehensive objective, that is we will be able to describe about different internal CPU bus organization and placement of components.

The core objective of the Three Bus Architecture unit is to help learners understand the internal organization and connectivity of CPU components through detailed discussions. This includes recognizing how various internal buses will affect component placement and data flow. By learning this, students will be equipped to design systems based on single, two, or three bus architectures.

Think of planning a city. Understanding how roads (buses) connect different neighborhoods (CPU components) allows for better layout and traffic flow. If you know where schools, parks, and shops (components) will be and how they connect, you can design better roads to facilitate transport and accessibility.

So, again I will first show you that is the three bus architecture, we have three buses A, B and C and these are the internal components like PC, register, ALU, decoder, instruction register etcetera.

In the Three Bus Architecture, there are three distinct buses labeled A, B, and C. Each bus serves a specific role in facilitating communication between the internal components of the CPU, such as the Program Counter (PC), registers, and the ALU. Bus A and Bus B are primarily responsible for transferring data from output registers to the ALU, while Bus C is designated for sending data back to the registers after processing.

Think of a communication system in a corporate office. If employees are divided into three teams (A, B, and C), teams A and B send information (like project updates) to a central point (the ALU), while team C is where the processed information is organized and stored for reference. This structured communication ensures clarity and efficiency in handling tasks.

So, mainly bus A and B are going to read the values and you are going to write the values sorry bus A and B are going to take the values from program counter, register files etcetera and the registers are going to read from bus C.

Bus A and B primarily read values from various sources like the Program Counter and registers. When data needs to be processed, it is fed into the ALU, while Bus C is used for output purposes, meaning data is written back to registers after processing. This mode of operation enables efficient data transfer and reduces the need for temporary storage within the architecture.

Consider a library system. Two aisles (Bus A and B) are specifically set up for returning books to the shelves, while the check-out desk (Bus C) is where books are logged out to patrons. This structure ensures that books move efficiently through their respective processes without unnecessary delays.

So, the memory data register it has four ports, it dumps the value to two register two lines A and B takes the input from line numbers C and also it can the bidirectional bus if you see it goes to the memory.

The Memory Data Register (MDR) in a Three Bus Architecture is designed with four ports to facilitate its function. It can transfer data to two buses (A and B) and receives input from one bus (C), enhancing the efficiency of data handling. This configuration minimizes delays often encountered in systems that rely on a single bus for input and output.

Think of a multi-lane highway. Here, multiple lanes (ports) allow many vehicles (data) to travel to different destinations (registers) simultaneously, compared to a single-lane road where only one vehicle can pass at a time. This multi-lane setup reduces congestion and improves travel time.

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