5.2.1. Example 4: Real World Processor Overview

As a fourth and last example we take the example of a real word processor which uses direct mapped cache. So, we take the example of in Intrinsity FastMATH processor which is a fast embedded processor based on MIPS architecture. The direct mapped cache organization of this processor is shown in the figure here. So, the cache uses separate 16 KB instruction and data caches there is the mem the organization has 16 KB instruction and data caches separate.

The Intrinsity FastMATH processor is an embedded processor that utilizes a direct mapped cache system to manage data efficiently. This particular organization uses dedicated cache for both instructions and data, each being 16 kilobytes (KB) in size. Direct mapped cache is a straightforward caching method where each block of main memory maps to exactly one cache line. This structure is beneficial for quick data retrieval as it minimizes the time taken to access frequently used instructions and data.

Imagine a library where each book must only be placed on a specific shelf (representing the cache lines), determined by the book's category (the program's data addresses). If another book of the same category is added, it must replace the existing book in that shelf (the original book gets pushed out), which illustrates how direct mapped cache replaces existing entries based on memory requests.

We have 32 bits per word. So, therefore, we have 4 byte words. We have 4K words in the cache ok and we have 16 word lines. So, each line contains 16 words. So, line size is 64 bytes. So, 16 words, each containing 4 bytes is 64 bytes and 64 bytes or 512 bits. We have a 8 bit wide line index. So, therefore, we have 256 lines in the cache. We have a 18 bit wide tag field. So, 218 possible blocks can map to each cache line ok.

In this cache organization, each word is 32 bits, which translates to 4 bytes per word. With a total of 4,096 words in the cache, the structure consists of lines, where each line can hold 16 words, resulting in a total line size of 64 bytes (or 512 bits). The line index is 8 bits wide, enabling the existence of 256 distinct lines in the cache. Additionally, an 18-bit tag field allows for a maximum of 262,144 (or 2^18) possible memory blocks to be stored in the cache.

Think of a large filing cabinet (the cache) divided into multiple drawers (the cache lines). Each drawer can only hold a limited number of files (the words). If you have a filing system that allows for multiple categories (the tags), you can quickly store and retrieve documents. The number of drawers and their size determines how quickly you can find what you're looking for, just like how the cache size and line size increase the speed of data access.

What are the steps for a read request on this? We send the address to cache, either the instruction cache or the data cache. Addresses are sent from the PC for the instruction cache and from the ALU for the data cache. On a hit, that means, the tag bits and valid bits match the tag bits and the valid bits match. On a hit when we have the tag bits and the valid bits matching, the data is made available on the data lines.

When the processor needs data, it sends an address to either the instruction cache or the data cache. This address comes from the program counter (PC) for instructions or the Arithmetic Logic Unit (ALU) for data. If the data is found (referred to as a 'hit'), the tag bits and valid bits that help verify the location match perfectly, allowing the desired data to be quickly fetched from the cache and delivered via the data lines.

Picture a waiter at a restaurant retrieving a food order from a specific table for a customer. The order (the address) originates from the kitchen (PC or ALU) who requests a dish. If the dish is currently on the table (the data cache hit), the waiter delivers it directly. However, if the dish isn't there, a different retrieval process involving the kitchen (main memory) would begin, illustrating cache hits and misses.

We have 16 words per line; that means, a line offset 16 words per line. So, we need to identify which word in the line is required. So, what we have? We have a line offset which is used to select which word in the line is desired by the memory. So, this line offset is used as a selector in a 16×1 mux and we have a 4 bit line access because we have 16 words in the line.

With each cache line containing 16 words, when the processor determines a hit has occurred, the system must then identify precisely which word among those in the line is being requested. To achieve this, a line offset was utilized. This offset acts as an index to select the appropriate word using a multiplexer (mux), which allows for efficient and immediate access to the specific word required for processing.

Consider a pizza with 16 slices (the words), where each slice can have a different topping. When a customer orders a topping (the specific word), the waiter checks which slice to serve (the line offset) using a distinct method (the mux). The faster this identification occurs, the quicker the customer receives their desired slice, similar to how line offsets streamline word retrieval in cache.

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