5.1.1. Understanding Cache Access

So, this figure shows the organization of a direct mapped cache. We see that the memory address consists of 𝑠 +𝑤 bits. The tag is 𝑠−𝑟 bits long. The cache line index, the cache index the cache is indexed by an 𝑟 bit length quantity and the each word within a particular block or line is identified by this word offset.

A direct mapped cache organizes memory addresses into a specific format. Each memory address has bits that represent different components: the total address length (s + w), the tag (s - r), and the cache index (r bits). The tag helps identify which main memory block corresponds to an entry in the cache, while the cache index directs where to look in the cache.

Think of a direct mapped cache as a library where each book (the memory block) has a special code (the address). The library has a unique shelf for certain categories (the cache index), and within those shelves, the books are sorted by specific codes (the tag). When you need a book, you first check the shelf for its category, then look for the specific code.

To identify whether a particular line is in cache or not, we first come to the line identified by these 𝑟 bits and then we compare the tag field with the 𝑠−𝑟 main memory bits. If this comparison is 1, we have a match and a hit in cache. When we have a hit in cache, we read the corresponding word in the cache.

When checking for a data item in the cache, the process involves using r bits to find the correct line in the cache and then comparing the stored tag for that line with the tag derived from the main memory address. If they match, it’s a cache hit, allowing direct access to the data. If they don't match, it results in a cache miss, requiring retrieval from the main memory.

Imagine you’re at a grocery store looking for a specific cereal. The store has aisles (cache lines) and each cereal box has a unique name (tag). You go to the aisle matching that name. If the cereal is there, you grab it right away; that’s a hit. If it’s not there, you have to go to the back room (main memory) to get it, which takes more time, and that’s a miss.

When we have a mismatch here, we have a cache miss and then we go to the main memory to find the particular block in main memory containing the word and then retrieve it into the cache.

A cache miss prompts the system to fetch the required data from the main memory. This involves locating and retrieving the entire block of memory that contains the requested word, then placing that block into the cache for faster future access. The process enhances overall performance by filling the cache with frequently accessed data.

Continuing with the grocery store analogy, if you ask an employee for a cereal, and it isn't on the shelf, they have to go to the stockroom to find it. They take a moment to retrieve the entire box (data block), not just a single piece. Once it's returned to the shelf (cache), it can be grabbed quickly next time.

For this cache we only have 8 blocks or 8 lines in the cache. We have 1 word per block so every word is a block. The initial state is all blank. We see that all the valid bits are N; that means, nothing has been accessed...

An example illustrates how a direct mapped cache functions with specific memory addresses. The system starts empty, and as memory addresses are accessed in a defined sequence, cache hits and misses occur. Each access leads to either storing data in the cache or fetching it from the main memory. Understanding this flow demonstrates the real-time implications of cache operations.

Consider the cache like a small pantry in your kitchen. Initially, it’s empty (no food). As you cook (make memory accesses) and bring in ingredients (data from memory addresses), sometimes you find what you need in the pantry (cache hit) and other times you have to go to the grocery store (main memory) to get it.

--