5.2. Examples of Direct Mapped Cache

So, this figure shows the organization of a direct mapped cache. We see that the memory address consists of 𝑠 +𝑤 bits. The tag is 𝑠−𝑟 bits long. The cache line index, the cache index the cache is indexed by an 𝑟 bit length quantity and each word within a particular block or line is identified by this word offset.

In a direct mapped cache, the organization is modeled based on several key components of the memory address. The memory address is made up of three parts: the tag, the cache line index, and the word offset. Specifically, 's' bits represent the total size of the memory address, 'w' is the number of bits used to identify individual words, 'r' is the number of bits that point to a specific line in the cache, and 's - r' gives us the bits needed to form the tag. This structure allows the cache to efficiently map memory addresses to cache lines, which optimizes the process of reading and writing data.

Imagine a library with a limited number of shelves (cache lines). Each book (memory block) has a unique ID (the main memory address). The ID is divided into parts – a broader category (the tag) and a specific shelf number (cache line index). When someone wants to find a book, they use the ID to find out which shelf to check. If they find the book (hit), they take it from that shelf; if not (miss), they must check other shelves or bring it in from storage.

To identify whether a particular line is in cache or not, we first look at the line identified by these 𝑟 bits and compare the tag field within the cache against the main memory's tag. A match means a cache hit, while a mismatch indicates a cache miss.

When the CPU accesses a memory address, it first checks the corresponding cache line indicated by the cache index bits (r bits). It then compares the tag bits from the cache with those from the main memory address. If the tags match, it indicates that the requested data is in the cache (cache hit), allowing for swift data retrieval. Conversely, if the tags do not match, it signifies that the data must be fetched from the slower main memory (cache miss). This comparison is crucial for optimizing access speed and efficiency.

Think of it like retrieving your favorite dish from the fridge (cache). If the dish is there (hit), you can quickly grab it. But if it’s not present (miss), you need to head to the pantry (main memory) to cook it. The quicker you can access the fridge (cache), the faster you can enjoy your meal!

For this cache, we only have 8 blocks or 8 lines in the cache. We have 1 word per block...We have the sequence of memory accesses 22, 26, 16, 3, 16, 18.

In the provided example, we start with an empty cache consisting of 8 lines. As we access memory addresses in sequence, we convert them to binary to identify which cache line they map to. For instance, accessing address 22, which in binary is 10110, indicates line 110 when taking the least significant 3 bits. Since the cache starts off empty, every memory access results in a miss initially until the cache starts getting populated. As we access different addresses, the cache updates based on whether hits or misses occur, demonstrating how data is retrieved and stored as memory accesses happen.

Imagine you start a new library. On the first day, all shelves are empty. Every time someone comes in to borrow a book (memory access), you must fetch it from the storage room (main memory). At first, every request results in a trip to the storage room (miss). As people request more and more books, you begin to store popular ones on the visible shelves (cache), so when someone comes back for a previously borrowed book, it's right there ready for them!

When a cache miss occurs, we go to the main memory to retrieve the particular block and then store it in the cache.

Upon encountering a cache miss, the system must fetch the required data from the main memory. It identifies the specific block of memory that contains the necessary data, retrieves it, and updates the cache with this new block. If the cache is already full, it may evict an existing block to make space for the new block, based on the mapping rules of the direct mapped cache. This process is crucial for maintaining efficient data access and ensuring that the most frequently used data remains quickly accessible.

Consider a library that has limited shelf space (cache). When a new book (data) comes in that patrons want, but the shelves are full, you must remove one book to make room (replace). This way, you always keep the most sought-after titles readily accessible, ensuring that patrons are happy with quick service, while older or less popular books may be stored away in the archives (main memory).

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