6.3.2. Assertion-Based Verification

Try these first

1. 1.

   Define what an assertion is in the context of verification.

   Hint

   Think about checks made during simulations.

2. 2.

   What does the acronym CAP signify in the context of assertions?

   Hint

   It relates to the expectation of assertions.

3. 3.

   What is the purpose of assertions in Verilog?

   • To generate random input
   • To specify design properties that must hold true
   • To simulate timing behavior

   Hint

   Think about what assertions validate.

4. 4.

   True or False: Assertions can only be used in formal verification.

   • True
   • False

   Hint

   Consider where assertions are applied.

5. 5.

   Create a set of assertions for a simple counter that should never exceed its maximum value.

   Hint

   Consider the role of the reset and the increment operation.

6. 6.

   Discuss how you would implement a formal verification strategy that includes assertions.

   Hint

   Think about how formal methods apply along with simulation.