16.1.1. Existing Instructions and New Instruction SUB M

These are the 3 Instruction we have designed and the code assigned is your 1, 2 and 5. Other codes are now still available to me. So, now we can design some more Instructions. So now, we are saying that already we have designed these 3 Instruction.

In this chunk, we introduce the current Instruction set of the processor. Three Instructions have been created, each associated with specific codes (1, 2, and 5). The text indicates that other codes are still available, providing an opportunity to create new Instructions as needed.

Think of this as a toolkit. You have three essential tools (the existing Instructions) that you regularly use. However, you realize that there are more tools in your toolkit (available codes), allowing you to add new functionalities when needed.

Now, we are saying that we are designing one more Instruction called SUB M, which means subtraction. So, what is this Instruction? This is basically nothing but Accumulator is equal to Accumulator minus contents of the Memory.

This chunk details the introduction of a new Instruction termed 'SUB M' for subtraction. The definition clarifies that this Instruction will update the Accumulator by subtracting the contents of a specified Memory location from it, effectively implementing a subtraction operation.

Imagine you have a piggy bank (the Accumulator) that holds your savings. If you want to buy a toy, you need to take some money out of the piggy bank. The 'SUB M' instruction works in the same way by removing (subtracting) a certain amount from what you currently have in the piggy bank.

We are going to give the Instruction format is same whatever we are going to design for all the Instruction it is going to follow this particular pattern.

This chunk emphasizes the consistency in the format of the new Instructions being developed. Regardless of the type, all Instructions (including the new SUB M instruction) will follow a standardized format which aids in their understanding and implementation.

Think of this as a recipe book where every recipe has the same structure: ingredients list, steps, and cooking time. This uniformity helps a cook easily follow different recipes without confusion.

Now I am going to give designing 4 more Instruction. This is a similar Instruction load, store sub m, but my reference is different initially we are talking about the memories now we are talking about the Registers.

The text outlines plans to add four more Instructions, highlighting a shift in focus from Memory references to Register references. This illustrates a broadening of the processor's capabilities by enabling more operations involving Registers alongside Memory.

Imagine you are a librarian. Initially, you are only cataloging books in a specific section (Memory). Now, you decide to start organizing a whole new section for magazines and journals (Registers) which expands your organizational capabilities.

If I am having say only 8 Registers that we are going to use say R0, R1 to R7 say these are the Registers. Then what will happen in that particular case we don’t require the 12 bits.

In this segment, we learn about the limited number of Registers (R0 to R7), which means less complexity in managing their references. This leads to a reduced need for instruction bits, making the process more efficient.

It’s like having a limited number of rooms in a house – you don’t need a huge directory when you only have a few places to remember. In this case, less complexity makes it easier to navigate.

If my Instruction is like that this is your opcode is your D and say it is your 007. Now, what it basically does it is an addition of R.

This chunk introduces another Instruction (SUB R), which is associated with an opcode and performs an addition operation involving the Register. This builds on our understanding of how Instructions are coded and executed.

Think of this as assigning specific tasks to your assistants. Each assistant knows exactly what to do (based on their Task Code), changing what they need to accomplish from just subtracting one value to adding different values from different Registers.

We are designing some more Instruction over here. So, this is INR is basically an increment and DEC is your decrement.

In this section, the focus is on creating two additional Instructions for incrementing (INR) and decrementing (DEC) values. These Instructions allow the processor to adjust values in Registers or Memory conveniently.

Imagine you are counting your earnings. Each time you make a sale, you say 'increment one' to add to your savings, and 'decrement one' when you give a refund. This is how the INR and DEC Instructions function in terms of managing values.

Now, here I am saying that opcode 0 is your JMP. It is a jump Instruction. It is a halt Instruction.

Finally, this section discusses the introduction of control Instructions like JMP for jump and HLT for halt. These Instructions are crucial for program flow control, dictating how and when the code execution progresses or stops.

Think of this as a traffic light system. The jump Instruction (JMP) signals cars when to go to a different road (change execution flow), while the halt Instruction (HLT) tells cars to stop until it's time to go again.

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