30.1. Examples of Multiple Bus Architecture

(Refer Slide Time: 36:52) Now, we are going to take two examples; in one example we will show that what are the advantages of having three buses and another case we will show that we do not get so much advantage, if you are considering a multiple bus architecture. Two extremes that means two different instructions we will take and show, but for most of the cases we are always going to have an advantage, because that is very obvious because if you have multiple buses things will go parallelly, but for one or two stray examples we can see where the advantage is not there in fact, you are having more hardware, but still the number of stages are not reducing.

This chunk introduces the concept of multiple bus architecture in computer systems. It mentions that there will be two examples to showcase the advantages and disadvantages of having multiple buses. The author indicates that while multiple buses allow for parallel processing, there might be a few scenarios where the benefits do not outweigh the costs – particularly, instances where hardware complexity increases but does not reduce the number of operational stages.

Consider a restaurant kitchen. In a kitchen with multiple chefs (buses), orders can be prepared simultaneously, allowing for faster service (parallel processing). However, if there are too many chefs with poorly defined roles (excessive hardware), they might get in each other's way and not actually speed up the process (lack of advantage), leading to inefficiency.

So, the first case we are going to take is add 𝑅 into 𝑅 . So, what is the thing? So, two variables 1 2 already available in 𝑅 and 𝑅 and then one you have to do it.

In this scenario, we focus on the instruction to add two registers, R1 and R2. The values in these registers are used for computation. The architecture allows efficient handling of this operation where both registers can be accessed simultaneously. This efficiency is critical in performance, where the ability to quickly fetch and execute instructions contributes to the overall processing speed.

Think of a librarian who can pull two books off two different shelves at the same time versus a librarian who has to go back and forth to different shelves. The first librarian can serve patrons faster by having simultaneous access (adding values from two registers), whereas the second librarian would be slower due to sequential access (single bus architecture).

So, first is you have to fetch the instruction. So, how do you fetch the instruction? Basically program counter output value will go to memory address register in, that is as simple as for single bus architecture then you put the memory in read mode.

This chunk explains the instruction fetching process in a computer architecture. The essential first step involves the program counter sending its value to the memory address register, which points to the location of the next instruction to be executed. This is crucial, as it sets the stage for either fetching or modifying data based on the instruction received.

Imagine finding a book in a library. First, you check the library catalog (program counter) to get the specific location of the book (memory address register). Once you know the location, you head directly to that aisle to get the book (fetch the instruction). Having a catalog makes this process efficient.

But if you look at a single bus architecture, we had another signal that is called 𝑍 . Because the output of program counter plus constant has to store in a separate temporary register which we call it Z or Y and we have to wait till this step is over then only you can write the value to the program counter.

In a single bus architecture, an additional register (like Z) is required to temporarily hold values while the program counter is updated. This leads to delays because computation must wait for the temporary storage action to complete before moving forward. In contrast, multiple buses allow direct calculations and updates, reducing latency and processing time.

Think of an assembly line in a factory that requires every part to be held in a buffer between stages. If one part (program counter) has to wait for its predecessor (the temporary register) to be processed before moving on, production slows down. In a more advanced setup with direct connections (multiple buses), parts can flow smoothly without unnecessary stops.

Now, let us see we have to now do the real addition? So, if you look at it. So, what is the addition? So, we are assuming that the two registers 𝑅 and 𝑅 already has the value, and the instruction that is 𝑅 𝑎𝑑𝑑 𝑅 ,𝑅 is going to the instruction register from instruction register it goes to the instruction decoder decoding has been done.

This chunk details the steps taken during the execution of the addition instruction after it has been fetched and decoded. The values from R1 and R2 are now processed by the instruction decoder, which prepares the necessary control signals and enables the addition to take place. The efficiency of multiple buses becomes apparent as both values can be accessed and processed simultaneously without unnecessary delays.

Consider a chef preparing a dish that requires multiple ingredients (values from registers). Using a well-organized kitchen (multiple buses), the chef can take all needed ingredients at once, speeding up the cooking process rather than fetching each ingredient one by one (single bus architecture).

So, now that means, what as I told you here we have to observe that basically here the signals are 𝑅 and 𝑅 , unlike in a single bus architecture you had something called 𝑅 𝑅 , here we have 1 2 out 2 out 1 out, R1 and R2 now why they are different because the register R2 can give the value to two different ports.

This chunk compares the signal flow for the multiple bus architecture with the single bus architecture. In a multiple bus architecture, each register, such as R1 and R2, can send its values across different ports simultaneously, allowing parallel processing. In contrast, the single bus architecture limits a register's ability to send its value at one time, resulting in longer operation periods.

If you have a shared taxi (single bus), it can only carry one passenger (register value) at a time. Conversely, if you have a carpool service (multiple buses), multiple passengers can be picked up at once, making for more efficient use of resources and faster travel times.

So, what is the instruction? The instruction says that load some value from memory location M to 𝑅 . So, the first stage is very similar program counter out memory register in, read, select 0 and add.

This example delves into the instruction for loading a value from memory into register R1. The operation mirrors the earlier cases, with the program counter providing the memory location to fetch the data, indicating simplified data management with multiple buses. This process ensures that memory operations like loading can execute efficiently without delay caused by temporary storage requirements.

Picture a postal worker retrieving mail (data) from different boxes (memory locations) at once. If they can fetch multiple letters directly (multiple buses), they save time compared to going back and forth to the same box each time (single bus).

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