Interrupts are a key feature of modern computer architectures, allowing the CPU to respond
immediately to specific events, bypassing its current task to handle more urgent ones. This
chapter covers how interrupt mechanisms work, their types, and their role in embedded systems
and general computing.

● Definition of Interrupts: An interrupt is a mechanism that allows a peripheral or
software event to disrupt the normal flow of a program, causing the CPU to temporarily
halt its current task and jump to a special function or handler (interrupt service routine, or
ISR).

● Purpose of Interrupts: Interrupts allow for more efficient CPU usage, enabling the
processor to handle time-sensitive events without constantly polling or checking for
changes.

Interrupts can be classified based on their source, nature, and priority. This section details the
different types of interrupts.

● Hardware Interrupts: These interrupts are generated by external hardware devices,
such as I/O peripherals (e.g., UART, timers, GPIO) or sensors. Hardware interrupts are
often used to signal the processor when data is ready to be processed or when an event
requires immediate attention.

● Software Interrupts: These interrupts are generated by software or the running program
to request the operating system’s attention or trigger a system call. They are often used
for tasks such as process scheduling, system calls, or debugging.

● Maskable Interrupts (IRQ): Maskable interrupts can be disabled or ignored by the
processor if they are not of high priority. These interrupts are typically used for general
I/O operations or peripheral events.

● Non-Maskable Interrupts (NMI): Non-maskable interrupts cannot be disabled or
ignored, as they indicate critical system errors or events that must be handled
immediately.

An Interrupt Service Routine (ISR) is a special function or piece of code that the processor
jumps to when an interrupt occurs. The ISR handles the event that triggered the interrupt.

● ISR Characteristics:
- Low-Latency Execution: An ISR should execute quickly to minimize the time
the CPU is interrupted from its main task.
- Interrupt Nesting: Some systems allow interrupts to occur while an ISR is
already being executed. This is known as interrupt nesting and requires careful
management to avoid stack overflow and context corruption.
- Context Saving: When an interrupt occurs, the processor must save its
current state (registers, program counter, etc.) to ensure that the program can
resume from the same point after the ISR completes.

● Structure of an ISR:
- Interrupt Acknowledgment: The ISR begins by acknowledging the interrupt and
clearing the interrupt flag to prevent the same interrupt from being triggered
repeatedly.
- Handling the Event: The main task of the ISR is to handle the event that caused
the interrupt, such as reading data from a peripheral or updating system
variables.
- Returning Control: Once the event is handled, the ISR ends by restoring the
previous processor state (i.e., context) and returning control to the main program.

Interrupt prioritization is important in systems with multiple interrupt sources. It determines the
order in which interrupts are handled, ensuring that more urgent tasks are given priority over
less critical ones.

● Priority Levels: Interrupts can be assigned priority levels. Higher-priority interrupts
preempt lower-priority ones, allowing critical events to be handled first.

● Interrupt Vectors: The interrupt vector is a table of memory addresses that point to the
ISRs for different interrupt sources. When an interrupt occurs, the processor uses the
vector to jump to the appropriate ISR.

● Interrupt Nesting: Some processors allow interrupts of higher priority to preempt an
ISR that is already running. This requires a mechanism to save the state of the current ISR
(using a stack) and later restore it.

There are different ways to manage and handle interrupts, each suited to different use cases in
embedded and general-purpose systems.

● Vectored Interrupts: In a vectored interrupt system, each interrupt has a unique entry in
the interrupt vector table, pointing directly to the corresponding ISR. This makes the
system fast and efficient when determining which interrupt service routine to execute.

● Non-Vectored Interrupts: Non-vectored interrupts do not have a specific address for
each interrupt. Instead, the ISR address is shared, and the processor must check the
interrupt source to determine which action to take.

● Interrupt Masking: The ability to mask (disable) specific interrupts allows the system to
control which interrupts are processed. This is useful for managing interrupt priorities
and avoiding unnecessary context switches during critical operations.

Interrupt latency is the time between the arrival of an interrupt and the start of its corresponding
ISR. Reducing interrupt latency is critical in time-sensitive applications, such as real-time
embedded systems.

● Factors Affecting Latency:
- Processor State: The time it takes for the processor to save its state before
jumping to the ISR.
- Interrupt Vectoring: If a vectored interrupt system is used, the time taken to look
up the interrupt vector contributes to latency.
- Interrupt Acknowledgment: The time required to acknowledge the interrupt and
clear the interrupt flag.

● Reducing Latency: To minimize latency, systems can be optimized by:
- Using a fast interrupt vector lookup.
- Reducing the number of instructions in the ISR.
- Implementing efficient interrupt handling mechanisms, such as direct memory
access (DMA) for peripheral data transfer.

Interrupts are essential in multitasking and real-time systems, where they are used for
time-critical task management, event handling, and resource sharing.

● Context Switching: In a multitasking environment, the operating system uses interrupts
to switch between tasks. A timer interrupt can trigger a context switch to change from
one process to another.

● Real-Time Operating Systems (RTOS): RTOSes rely heavily on interrupts to meet
strict timing requirements. They use interrupts to trigger context switches, handle
timeouts, and schedule periodic tasks.

● Priority-Based Scheduling: In real-time systems, interrupt handling and scheduling are
typically based on priorities. Higher-priority tasks or interrupts are handled before
lower-priority ones, ensuring timely processing.

Some systems allow interrupt nesting, where a higher-priority interrupt can preempt a
lower-priority ISR. This section explains how nested interrupts work and how to manage them.

● Interrupt Nesting: Interrupts with higher priorities can interrupt an ISR that is
already executing. This allows more urgent tasks to be processed immediately.

● Stack Management: To support nested interrupts, the system must use a stack
to store the state of each ISR, ensuring that lower-priority ISRs are resumed after
the higher-priority ones complete.

● Interrupt Priority Masking: The ability to mask or disable lower-priority interrupts during
the execution of a high-priority ISR ensures that critical tasks are not delayed by less
important events.

In more complex systems, interrupt controllers manage the distribution and prioritization of
interrupts. These controllers handle the distribution of interrupt signals and determine which
interrupt to process.

● Programmable Interrupt Controllers (PIC): PICs allow for the dynamic assignment of
interrupt priorities and enable finer control over interrupt handling.

● Advanced Interrupt Controllers (APIC): In more advanced systems, the APIC
(Advanced Programmable Interrupt Controller) can handle multiple interrupt sources with
enhanced features, including priority management, masking, and interrupt routing.

● Nested Vectored Interrupt Controllers (NVIC): In ARM Cortex-M processors, the NVIC
allows for interrupt prioritization and efficient handling of interrupt sources with low
latency. The NVIC supports interrupt grouping and nested interrupts, ensuring that
high-priority tasks are processed first.

Debugging systems with interrupts can be challenging due to the asynchronous nature of
interrupts and the potential for race conditions.

● Debugging Strategies:
- ISR Logging: Logging the entry and exit of each ISR can help debug
interrupt-related issues.
- Breakpoint and Watchpoint: Using breakpoints in the ISR or interrupt handlers
can help track execution flow.
- Stack Analysis: Analyzing the interrupt stack can identify issues related to
interrupt nesting or context switching.

Interrupt mechanisms are a fundamental part of modern computing, enabling systems to
respond promptly to external events and efficiently manage resources. Whether in embedded
systems, multitasking environments, or real-time operating systems, interrupts ensure that the
system operates with responsiveness and efficiency. Understanding interrupt types, latency, and
management is crucial for designing reliable and time-sensitive applications.