Layout Design and Verification of Basic Combinational CMOS Logic Gates
This lab module guides students through the design and verification of combinational CMOS logic gates, specifically focusing on the 2-input NAND and NOR gates. It emphasizes extending layout expertise, mastering complex routing, adhering to design rules, and understanding performance-driven layouts. Additionally, it covers the importance of physical verification and post-layout simulation to ensure functional correctness and performance analysis of the designs.
Sections
Navigate through the learning materials and practice exercises.
What we have learnt
- Students can apply full-custom mask layout design principles to 2-input NAND and NOR gates.
- Effective routing connections are critical for multi-transistor gate layouts.
- Comprehensive physical verification is essential for identifying and correcting errors, ensuring manufacturability and accuracy.
Key Concepts
- -- Combinational Logic Gates
- Logic gates (like NAND and NOR) whose output strictly depends on current input values at any point in time.
- -- Design Rule Check (DRC)
- A verification process that checks the layout against prescribed geometric rules to ensure manufacturability.
- -- Layout Versus Schematic (LVS)
- A verification method that compares the physical layout's electrical connectivity with that of the original schematic to ensure they match.
- -- Parasitic Extraction
- The process that identifies and incorporates unintended parasitic capacitances and resistances from the layout into the simulation to provide a more accurate performance prediction.
- -- Common Centroid Layout
- A layout technique where multiple transistors are interleaved around a common center to minimize variation due to manufacturing imperfections.
Additional Learning Materials
Supplementary resources to enhance your learning experience.